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com.minres.coredsl.tests/src/com/minres/coredsl/tests
com.minres.coredsl/src/com/minres/coredsl/analysis Expand file tree Collapse file tree 3 files changed +3062
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lines changed Original file line number Diff line number Diff line change @@ -257,4 +257,29 @@ class CoreDslParsingTest {
257257 assertTrue(issues. filter[it . severity == Severity . ERROR ]. isEmpty())
258258 assertTrue(issues. size == 1 )
259259 }
260+ @Test
261+ def void unaryExpressionFromIndexed() {
262+ val content = ' ' '
263+ InstructionSet TestISA {
264+ architectural_state {
265+ unsigned int XLEN;
266+ register unsigned<XLEN> X[32];
267+ }
268+ instructions {
269+ FOO {
270+ encoding: 0b0000000 :: rs2[4:0] :: rs1[4:0] :: 0b000 :: rd[4:0] :: 0b1111011;
271+ behavior: {
272+ if (rd != 0) {
273+ X[rd][15: 0] = (unsigned<16>)(-X[rs1][15: 0]);
274+ }
275+ }
276+ }
277+ }
278+ }
279+ ' ' ' . parse
280+ val issues = validator. validate(content)
281+ for (iss : issues) println(iss)
282+ assertTrue(issues. filter[it . severity == Severity . ERROR ]. isEmpty())
283+ assertTrue(issues. size == 0 )
284+ }
260285}
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