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RKSimonMixedMatched
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[X86] combineBitcastvxi1 - bail out on soft-float targets (llvm#161704)
combineBitcastvxi1 is sometimes called pre-legalization, so don't introduce X86ISD::MOVMSK nodes when vector types aren't legal Fixes llvm#161693
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llvm/lib/Target/X86/X86ISelLowering.cpp

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@@ -45457,7 +45457,8 @@ static SDValue combineBitcastvxi1(SelectionDAG &DAG, EVT VT, SDValue Src,
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const SDLoc &DL,
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const X86Subtarget &Subtarget) {
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EVT SrcVT = Src.getValueType();
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if (!SrcVT.isSimple() || SrcVT.getScalarType() != MVT::i1)
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if (Subtarget.useSoftFloat() || !SrcVT.isSimple() ||
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SrcVT.getScalarType() != MVT::i1)
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return SDValue();
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// Recognize the IR pattern for the movmsk intrinsic under SSE1 before type

llvm/test/CodeGen/X86/pr161693.ll

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@@ -0,0 +1,40 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
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define void @PR161693() #0 {
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; CHECK-LABEL: PR161693:
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; CHECK: # %bb.0: # %start
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; CHECK-NEXT: movzbl (%rax), %eax
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; CHECK-NEXT: andb $-33, %al
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; CHECK-NEXT: addb $-71, %al
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; CHECK-NEXT: .p2align 4
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; CHECK-NEXT: .LBB0_1: # %loop
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; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: cmpb $-6, %al
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; CHECK-NEXT: setb %cl
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; CHECK-NEXT: leal (%rcx,%rcx), %edx
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; CHECK-NEXT: orb %cl, %dl
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; CHECK-NEXT: leal (,%rdx,4), %ecx
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; CHECK-NEXT: orb %dl, %cl
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; CHECK-NEXT: je .LBB0_1
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; CHECK-NEXT: # %bb.2: # %exit
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; CHECK-NEXT: retq
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start:
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br label %loop
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loop:
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%.val.i.i89 = load <16 x i8>, ptr poison, align 1
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%.not49.i = icmp ult <16 x i8> zeroinitializer, splat (i8 -10)
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%i = and <16 x i8> %.val.i.i89, splat (i8 -33)
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%i1 = add <16 x i8> %i, splat (i8 -71)
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%.not51.i = icmp ult <16 x i8> %i1, splat (i8 -6)
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%.not46.i = and <16 x i1> %.not49.i, %.not51.i
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%i2 = bitcast <16 x i1> %.not46.i to i16
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%_0.i = icmp eq i16 %i2, 0
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br i1 %_0.i, label %loop, label %exit
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exit:
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ret void
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}
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attributes #0 = { "target-features"="+soft-float" }

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