Added one more testbench on other type of messbauer_generator plus screens of how it works

Author: EvilLord666

.gitignore

@@ -1,9 +1,14 @@
 # Xilinx ISE Generated files
 \messbauer_generator.*
-\messbauer_generator_*
+messbauer_generator_*
 par_usage_statistics*
 webtalk_pn*
 _ngo*
 _xmsgs*
 \*xst\*
-xlnx_auto_0_xdb
+xlnx_auto_0_xdb
+\isim\*
+*.log
+filter.filter
+fuse.xmsgs
+xilinxsim.ini

docs/messbauer_generator/channel_after/channel_time(512 channels).png

@@ -0,0 +1,62 @@
+`timescale 1ns / 1ps
+
+////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer:
+//
+// Create Date:   20:36:12 08/30/2017
+// Design Name:   messbauer_generator
+// Module Name:   E:/PLD/MessbauerTestEnvironment/messbaue_test_environment/tests/messbauer_generator_testbench_channelafter.v
+// Project Name:  messbaue_test_environment
+// Target Device:  
+// Tool versions:  
+// Description: 
+//
+// Verilog Test Fixture created by ISE for module: messbauer_generator
+//
+// Dependencies:
+// 
+// Revision:
+// Revision 1.0
+// Additional Comments:
+// 
+////////////////////////////////////////////////////////////////////////////////
+
+module messbauer_generator_testbench_channelafter;
+
+	// Inputs
+	reg aclk;
+	reg areset_n;
+
+	// Outputs
+	wire start;
+	wire channel;
+
+	// Instantiate the Unit Under Test (UUT)
+	messbauer_generator # (.CHANNEL_TYPE(2))  // channel after measurements
+	uut 
+	(
+		.aclk(aclk), 
+		.areset_n(areset_n), 
+		.start(start), 
+		.channel(channel)
+	);
+
+	initial begin
+		// Initialize Inputs
+		aclk = 0;
+		areset_n = 0;
+
+		// Wait 100 ns for global reset to finish
+		#100;
+      areset_n = 1;
+		// Add stimulus here
+	end
+	
+	always 
+	begin
+	    #20 aclk = ~aclk;
+	end
+      
+endmodule
+

docs/messbauer_generator/channel_after/first_channel_start.png

@@ -0,0 +1,62 @@
+`timescale 1ns / 1ps
+
+////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer:
+//
+// Create Date:   11:51:47 08/30/2017
+// Design Name:   messbauer_generator
+// Module Name:   ./messbaue_test_environment/tests/messbauer_generator_testbench_channelsync.v
+// Project Name:  messbaue_test_environment
+// Target Device:  
+// Tool versions:  
+// Description: 
+//
+// Verilog Test Fixture created by ISE for module: messbauer_generator
+//
+// Dependencies:
+// 
+// Revision:
+// Revision 1.0
+// Additional Comments:
+// 
+////////////////////////////////////////////////////////////////////////////////
+
+module messbauer_generator_testbench_channelsync;
+
+	// Inputs
+	reg aclk;
+	reg areset_n;
+
+	// Outputs
+	wire start;
+	wire channel;
+
+	// Instantiate the Unit Under Test (UUT)
+	messbauer_generator # (.CHANNEL_TYPE(1))  // Start and channel are synchronous
+	uut 
+	(
+		.aclk(aclk), 
+		.areset_n(areset_n), 
+		.start(start), 
+		.channel(channel)
+	);
+
+	initial begin
+		// Initialize Inputs
+		aclk = 0;
+		areset_n = 0;
+
+		// Wait 100 ns for global reset to finish
+		#100;
+      areset_n = 1;
+		// Add stimulus here
+	end
+	
+	always 
+	begin
+	    #20 aclk = ~aclk;
+	end
+      
+endmodule
+