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EvilLord666EvilLord666
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Fixes in diff_discriminator, implementation of top module
1 parent f1a3fdc commit c8aab71

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6 files changed

+186
-121
lines changed

6 files changed

+186
-121
lines changed

‎docs/messbauer_generator/diff_discriminator/diff_discriminator_emulation.png‎

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‎docs/messbauer_generator/diff_discriminator/diff_discriminator_emulation_enlarged.png‎

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‎messbauer_test_environment/src/__Previews/messbauer_test_environment.vPreview‎

Lines changed: 14 additions & 0 deletions
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‎messbauer_test_environment/src/messbauer_diff_discriminator_signals.v‎

Lines changed: 80 additions & 74 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
`timescale 1ns / 1ps
22
//////////////////////////////////////////////////////////////////////////////////
3-
// Company:
4-
// Engineer:
3+
// Company: MossbauerLab
4+
// Engineer: EvilLord666 (Ushakov MV)
55
//
66
// Create Date: 21:01:28 08/30/2017
77
// Design Name: messbauer_test_environment
@@ -45,6 +45,7 @@
4545
localparam PAUSE_DURATION = 4;
4646

4747
reg enable;
48+
reg first_enable;
4849
reg[7:0] clk_counter;
4950
reg[7:0] impulse_counter;
5051
reg[7:0] total_impulse_counter;
@@ -54,86 +55,91 @@
5455

5556
always @(posedge aclk)
5657
begin
57-
if(~areset_n)
58-
begin
59-
clk_counter <= 0;
60-
impulse_counter <= 0;
61-
total_impulse_counter <= 0;
62-
state <= INITIAL_STATE;
63-
lower_threshold <= 0;
64-
upper_threshold <= 0;
65-
enable <= 1;
66-
impulse_rejected <= 1;
67-
end
68-
else
69-
begin
70-
if(enable)
71-
begin
72-
clk_counter <= clk_counter + 1;
73-
case (state)
74-
INITIAL_STATE:
75-
begin
76-
clk_counter <= 0;
77-
state <= LOWER_THRESHOLD_HIGH_PHASE;
78-
impulse_rejected <= 0;
79-
period_done <= 0;
80-
end
81-
LOWER_THRESHOLD_HIGH_PHASE:
82-
begin
83-
lower_threshold <= 1;
84-
if(clk_counter == 1)
85-
begin
86-
// check should we generate upper
87-
if(impulse_counter <= IMPULSES_FOR_SELECTION)
88-
state <= LOWER_THRESHOLD_LOW_PHASE;
89-
else state <= UPPER_THRESHOLD_HIGH_PHASE;;
90-
end
91-
end
92-
UPPER_THRESHOLD_HIGH_PHASE:
93-
begin
94-
impulse_rejected <= 1;
95-
upper_threshold <= 1;
96-
if(clk_counter == UPPER_THRESHOLD_DURATION + 1)
97-
state <= UPPER_THRESHOLD_LOW_PHASE;
98-
end
99-
UPPER_THRESHOLD_LOW_PHASE:
100-
begin
101-
state <= LOWER_THRESHOLD_LOW_PHASE;
102-
upper_threshold <= 0;
103-
end
104-
LOWER_THRESHOLD_LOW_PHASE:
58+
if(~areset_n)
59+
begin
60+
clk_counter <= 0;
61+
impulse_counter <= 0;
62+
total_impulse_counter <= 0;
63+
state <= INITIAL_STATE;
64+
lower_threshold <= 0;
65+
upper_threshold <= 0;
66+
first_enable <= 1;
67+
impulse_rejected <= 1;
68+
end
69+
else
70+
begin
71+
if(first_enable || enable)
72+
begin
73+
clk_counter <= clk_counter + 1;
74+
case (state)
75+
INITIAL_STATE:
76+
begin
77+
clk_counter <= 0;
78+
state <= LOWER_THRESHOLD_HIGH_PHASE;
79+
impulse_rejected <= 0;
80+
period_done <= 0;
81+
end
82+
LOWER_THRESHOLD_HIGH_PHASE:
83+
begin
84+
lower_threshold <= 1;
85+
if(clk_counter == 1)
10586
begin
106-
lower_threshold <= 0;
107-
if(clk_counter >= LOWER_THRESHOLD_DURATION)
108-
begin
109-
if(impulse_rejected == 0)
110-
impulse_counter <= impulse_counter + 1;
111-
total_impulse_counter <= total_impulse_counter + 1;
112-
if(total_impulse_counter < IMPULSES_PER_CHANNEL)
113-
state <= INITIAL_STATE;
114-
else state <= FINAL_STATE;
115-
end
87+
// check should we generate upper
88+
if(impulse_counter <= IMPULSES_FOR_SELECTION)
89+
state <= LOWER_THRESHOLD_LOW_PHASE;
90+
else state <= UPPER_THRESHOLD_HIGH_PHASE;;
91+
end
92+
end
93+
UPPER_THRESHOLD_HIGH_PHASE:
94+
begin
95+
impulse_rejected <= 1;
96+
upper_threshold <= 1;
97+
if(clk_counter == UPPER_THRESHOLD_DURATION + 1)
98+
state <= UPPER_THRESHOLD_LOW_PHASE;
99+
end
100+
UPPER_THRESHOLD_LOW_PHASE:
101+
begin
102+
state <= LOWER_THRESHOLD_LOW_PHASE;
103+
upper_threshold <= 0;
104+
end
105+
LOWER_THRESHOLD_LOW_PHASE:
106+
begin
107+
lower_threshold <= 0;
108+
if(clk_counter >= LOWER_THRESHOLD_DURATION)
109+
begin
110+
if(impulse_rejected == 0)
111+
impulse_counter <= impulse_counter + 1;
112+
total_impulse_counter <= total_impulse_counter + 1;
113+
if(total_impulse_counter < IMPULSES_PER_CHANNEL)
114+
state <= INITIAL_STATE;
115+
else state <= FINAL_STATE;
116116
end
117-
FINAL_STATE:
118-
begin
119-
impulse_counter <= 0;
120-
total_impulse_counter <= 0;
121-
period_done <= 1;
122-
end
123-
default:
124-
begin
125-
end
126-
endcase
127-
end
128-
else
129-
state <= INITIAL_STATE;
117+
end
118+
FINAL_STATE:
119+
begin
120+
impulse_counter <= 0;
121+
total_impulse_counter <= 0;
122+
period_done <= 1;
123+
first_enable <= 0;
124+
end
125+
default:
126+
begin
127+
end
128+
endcase
129+
end
130+
else state <= INITIAL_STATE;
130131
end
131132
end
132133

133-
always @(posedge channel)
134+
always @(posedge channel or negedge areset_n)
134135
begin
136+
if(~areset_n)
137+
enable = 0;
138+
else
139+
begin
135140
if(period_done)
136141
enable = ~enable;
142+
end
137143
end
138144

139145
endmodule

‎messbauer_test_environment/src/messbauer_generator.v‎

Lines changed: 47 additions & 47 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
`timescale 1ns / 1ps
22
//////////////////////////////////////////////////////////////////////////////////
3-
// Company: MossbauerLab
4-
// Engineer: EvilLord666 (Ushakov MV)
3+
// Company: MossbauerLab
4+
// Engineer: EvilLord666 (Ushakov MV)
55
//
66
// Create Date: 23:57:05 08/28/2017
77
// Design Name:
@@ -26,17 +26,17 @@
2626
module messbauer_generator #
2727
(
2828
//parameter GCLK_FREQUENCY = 50000000, // maybe will be used in future
29-
parameter GCLK_PERIOD = 20, // nanoseconds
29+
parameter GCLK_PERIOD = 20, // nanoseconds
3030
parameter START_DURATION = 50, // number of GCLK periods (aclk port), 1 clock is 20ns
3131
parameter CHANNEL_NUMBER = 512, // is a degree of 2 i.e. 128, 256, 512, 1024 and others smaller than 4096 !
3232
parameter CHANNEL_DURATION = (16 * (`MAX_CHANNEL_NUMBER / CHANNEL_NUMBER)) * 1000 / (2 *GCLK_PERIOD), // channel duration in clock periods
33-
parameter CHANNEL_TYPE = `CHANNEL_AFTER_MEASURE // options are 1) START_AND_CHANNEL_SYNC or 2) CHANNEL_AFTER_MEASURE
33+
parameter CHANNEL_TYPE = `CHANNEL_AFTER_MEASURE // options are 1) START_AND_CHANNEL_SYNC or 2) CHANNEL_AFTER_MEASURE
3434
)
3535
(
3636
input wire aclk,
37-
input wire areset_n,
38-
output reg start,
39-
output reg channel
37+
input wire areset_n,
38+
output reg start,
39+
output reg channel
4040
);
4141

4242
localparam CHANNEL_GUARD_DURATION = CHANNEL_DURATION - 4 * (1000 / GCLK_PERIOD); // for switch before 4 us
@@ -55,63 +55,63 @@
5555
always @(posedge aclk)
5656
begin
5757
if(~areset_n)
58-
begin
59-
start <= 1'b1;
60-
channel <= 1'b1;
61-
clk_counter <= 8'b0;
62-
state <= INITIAL_STATE;
63-
end
64-
else
65-
begin
66-
case (state)
67-
INITIAL_STATE:
68-
begin
69-
state <= START_LOW_PHASE_STATE;
70-
clk_counter <= 0;
71-
end
72-
START_LOW_PHASE_STATE:
73-
begin
74-
start <= 0;
58+
begin
59+
start <= 1'b1;
60+
channel <= 1'b1;
61+
clk_counter <= 8'b0;
62+
state <= INITIAL_STATE;
63+
end
64+
else
65+
begin
66+
case (state)
67+
INITIAL_STATE:
68+
begin
69+
state <= START_LOW_PHASE_STATE;
70+
clk_counter <= 0;
71+
end
72+
START_LOW_PHASE_STATE:
73+
begin
74+
start <= 0;
7575
channel_counter <= 0;
7676
if(CHANNEL_TYPE == `START_AND_CHANNEL_SYNC && clk_counter == 0)
7777
channel <= 0;
7878
clk_counter <= clk_counter + 1;
7979
if(clk_counter == START_DURATION)
80-
state <= CHANNEL_GENERATION_STATE;
81-
end
82-
CHANNEL_GENERATION_STATE:
83-
begin
84-
start <= 1;
85-
clk_counter <= clk_counter + 1;
80+
state <= CHANNEL_GENERATION_STATE;
81+
end
82+
CHANNEL_GENERATION_STATE:
83+
begin
84+
start <= 1;
85+
clk_counter <= clk_counter + 1;
8686
if(clk_counter == CHANNEL_GUARD_DURATION)
8787
begin
8888
channel <= ~channel;
8989
end
9090
if(clk_counter == CHANNEL_DURATION)
9191
begin
9292
channel <= ~channel;
93-
channel_counter <= channel_counter + 1;
94-
clk_counter <= 0;
95-
if((channel_counter == CHANNEL_NUMBER - 1 && CHANNEL_TYPE != `START_AND_CHANNEL_SYNC) ||
96-
(channel_counter == CHANNEL_NUMBER && CHANNEL_TYPE == `START_AND_CHANNEL_SYNC))
97-
begin
98-
state <= START_HIGH_PHASE_STATE;
99-
end
93+
channel_counter <= channel_counter + 1;
94+
clk_counter <= 0;
95+
if((channel_counter == CHANNEL_NUMBER - 1 && CHANNEL_TYPE != `START_AND_CHANNEL_SYNC) ||
96+
(channel_counter == CHANNEL_NUMBER && CHANNEL_TYPE == `START_AND_CHANNEL_SYNC))
97+
begin
98+
state <= START_HIGH_PHASE_STATE;
99+
end
100100
end
101-
end
102-
START_HIGH_PHASE_STATE:
103-
begin
104-
start <= 1;
101+
end
102+
START_HIGH_PHASE_STATE:
103+
begin
104+
start <= 1;
105105
channel <= 1;
106106
clk_counter <= clk_counter + 1;
107107
if(clk_counter == START_HIGH_PHASE_DURATION)
108108
state <= INITIAL_STATE;
109-
end
110-
default:
111-
begin
112-
end
113-
endcase
114-
end
109+
end
110+
default:
111+
begin
112+
end
113+
endcase
114+
end
115115
end
116116

117117
endmodule

‎messbauer_test_environment/src/messbauer_test_environment.v‎

Lines changed: 45 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,45 @@
1+
`timescale 1ns / 1ps
2+
//////////////////////////////////////////////////////////////////////////////////
3+
// Company: MossbauerLav
4+
// Engineer: EvilLord666 (Ushakov MV)
5+
//
6+
// Create Date: 11:24:46 09/19/2017
7+
// Design Name:
8+
// Module Name: messbauer_test_environment
9+
// Project Name:
10+
// Target Devices: Spartan 6
11+
// Tool versions: Xilinx ISE 14.7
12+
// Description:
13+
//
14+
// Dependencies:
15+
//
16+
// Revision:
17+
// Revision 1.0
18+
// Additional Comments:
19+
//
20+
//////////////////////////////////////////////////////////////////////////////////
21+
module messbauer_test_environment
22+
(
23+
input aclk, // 50 MHz GCLK, T8
24+
input areset_n, // L3 as Button
25+
// Left Side of AX309 Board
26+
output v1_channel, // H15
27+
output v1_start, // F16
28+
output v1_lower_threshold, // C10
29+
output v1_upper_threshold, // D16
30+
// Right Side of AX309 Board
31+
output v2_channel, // L16
32+
output v2_start, // M15
33+
output v2_lower_threshold, // R16
34+
output v2_upper_threshold // T15
35+
);
36+
37+
// Left Side (v1) interface
38+
messbauer_generator #(.CHANNEL_NUMBER(512), .CHANNEL_TYPE(1)) v1_generator(.aclk(aclk), .areset_n(areset_n), .start(v1_start), .channel(v1_channel));
39+
messbauer_diff_discriminator_signals v1_diff_discriminator(.aclk(aclk), .areset_n(areset_n), .channel(v1_channel), .lower_threshold(v1_lower_threshold), .upper_threshold(v1_upper_threshold));
40+
41+
// Right Side (v1) interface
42+
messbauer_generator #(.CHANNEL_NUMBER(512), .CHANNEL_TYPE(1)) v2_generator(.aclk(aclk), .areset_n(areset_n), .start(v2_start), .channel(v2_channel));
43+
messbauer_diff_discriminator_signals v2_diff_discriminator(.aclk(aclk), .areset_n(areset_n), .channel(v2_channel), .lower_threshold(v2_lower_threshold), .upper_threshold(v2_upper_threshold));
44+
45+
endmodule

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