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1 | 1 | `timescale 1ns / 1ps |
2 | 2 | ////////////////////////////////////////////////////////////////////////////////// |
3 | | -// Company: MossbauerLav |
| 3 | +// Company: MossbauerLab |
4 | 4 | // Engineer: EvilLord666 (Ushakov MV) |
5 | 5 | // |
6 | 6 | // Create Date: 11:24:46 09/19/2017 |
@@ -34,12 +34,33 @@ module messbauer_test_environment |
34 | 34 | output v2_upper_threshold // T14 |
35 | 35 | ); |
36 | 36 |
|
| 37 | +reg internal_reset; |
| 38 | +reg [5:0] counter; |
| 39 | + |
37 | 40 | // Left Side (v1) interface |
38 | | -messbauer_generator #(.CHANNEL_NUMBER(512), .CHANNEL_TYPE(1)) v1_generator(.aclk(global_clock), .areset_n(global_reset), .start(v1_start), .channel(v1_channel)); |
39 | | -messbauer_diff_discriminator_signals v1_diff_discriminator(.aclk(global_clock), .areset_n(global_reset), .channel(v1_channel), .lower_threshold(v1_lower_threshold), .upper_threshold(v1_upper_threshold)); |
| 41 | +messbauer_generator #(.CHANNEL_NUMBER(512), .CHANNEL_TYPE(1)) v1_generator(.aclk(global_clock), .areset_n(global_reset & internal_reset), .start(v1_start), .channel(v1_channel)); |
| 42 | +messbauer_diff_discriminator_signals v1_diff_discriminator(.aclk(global_clock), .areset_n(global_reset & internal_reset), .channel(v1_channel), .lower_threshold(v1_lower_threshold), .upper_threshold(v1_upper_threshold)); |
40 | 43 |
|
41 | 44 | // Right Side (v1) interface |
42 | | -messbauer_generator #(.CHANNEL_NUMBER(512), .CHANNEL_TYPE(2)) v2_generator(.aclk(global_clock), .areset_n(global_reset), .start(v2_start), .channel(v2_channel)); |
43 | | -messbauer_diff_discriminator_signals v2_diff_discriminator(.aclk(global_clock), .areset_n(global_reset), .channel(v2_channel), .lower_threshold(v2_lower_threshold), .upper_threshold(v2_upper_threshold)); |
| 45 | +messbauer_generator #(.CHANNEL_NUMBER(512), .CHANNEL_TYPE(2)) v2_generator(.aclk(global_clock), .areset_n(global_reset & internal_reset), .start(v2_start), .channel(v2_channel)); |
| 46 | +messbauer_diff_discriminator_signals v2_diff_discriminator(.aclk(global_clock), .areset_n(global_reset & internal_reset), .channel(v2_channel), .lower_threshold(v2_lower_threshold), .upper_threshold(v2_upper_threshold)); |
| 47 | + |
| 48 | +always @(posedge global_clock) |
| 49 | +begin |
| 50 | + if(~global_reset) |
| 51 | + begin |
| 52 | + internal_reset <= 1; |
| 53 | + counter <= 0; |
| 54 | + end |
| 55 | + if(counter < 16) |
| 56 | + counter <= counter + 1'b1; |
| 57 | + if(counter >= 16 && counter < 32) |
| 58 | + begin |
| 59 | + counter <= counter + 1'b1; |
| 60 | + internal_reset <= 0; |
| 61 | + end |
| 62 | + if(counter == 32) |
| 63 | + internal_reset <= 1; |
| 64 | +end |
44 | 65 |
|
45 | 66 | endmodule |
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