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corrodiscorrodis
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Merge pull request #26 from Mu2e/scorrodi/FebII
FEB II Dev Work
2 parents 04b7b77 + ef7c188 commit d375ae7

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11 files changed

+1308
-65
lines changed

11 files changed

+1308
-65
lines changed

‎otsdaq-mu2e-crv/ArtModules/CrvOtsDqm_module.cc‎

Lines changed: 502 additions & 0 deletions
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‎otsdaq-mu2e-crv/ArtModules/CrvPrint_module.cc‎

Lines changed: 437 additions & 0 deletions
Large diffs are not rendered by default.

‎otsdaq-mu2e-crv/CMakeLists.txt‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,2 +1,3 @@
11
add_subdirectory(FEInterfaces)
22
add_subdirectory(ArtModules)
3+
add_subdirectory(TablePlugins)

‎otsdaq-mu2e-crv/FEInterfaces/FEBII_Registers.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -55,6 +55,7 @@ enum Register : uint16_t
5555
GateOnOffSpill = 0x1307, // 6.25ns, default 16
5656
GateOffOffSpill = 0x1308, // 6.25ns, default 1792
5757
LEDOn = 0x1318, // 6.25ns, default
58+
PortAll = 0x1329, // set port for all FPGAs
5859

5960
// broadcast to all FEBs on ROC
6061
AllFEB = 0x3000,

‎otsdaq-mu2e-crv/FEInterfaces/ROCCosmicRayVetoInterface.h‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -54,12 +54,12 @@ class ROCCosmicRayVetoInterface : public ROCCoreVInterface
5454

5555
// CRV ROC specific functions
5656
void Reset();
57-
void RocConfigure(bool gr=false, uint16_t grn=0, uint16_t uBoffset = 0x0);
57+
void RocConfigure(bool gr=false, uint16_t grn=0, uint16_t uBoffset = 0x0, uint16_t timeout = 0xffff);
5858
void FebConfigure(bool useOtsConfig = true);
5959
void ResetRxBuffers();
6060
void SetMarkerSync(bool enable=true);
6161
int16_t Realign(int sleep_uc = 1000);
62-
void ResetPLL(int sleep_us = 1000);
62+
void ResetPLL(int sleep_us = 1000, bool allPorts = false);
6363

6464
uint16_t ReadAFE(uint16_t fpga, uint16_t afe_no, uint16_t reg);
6565
// CRV FEB specific functions
@@ -107,6 +107,8 @@ class ROCCosmicRayVetoInterface : public ROCCoreVInterface
107107
void FebIITrigBaselines (__ARGS__);
108108
void SetInputMask (__ARGS__);
109109
// clang-format on
110+
private:
111+
bool gr;
110112
};
111113

112114
} // namespace ots

‎otsdaq-mu2e-crv/FEInterfaces/ROCCosmicRayVetoInterface_interface.cc‎

Lines changed: 137 additions & 63 deletions
Original file line numberDiff line numberDiff line change
@@ -20,7 +20,7 @@ ROCCosmicRayVetoInterface::ROCCosmicRayVetoInterface(
2020
const std::string& rocUID,
2121
const ConfigurationTree& theXDAQContextConfigTree,
2222
const std::string& theConfigurationPath)
23-
: ROCCoreVInterface(rocUID, theXDAQContextConfigTree, theConfigurationPath)
23+
: ROCCoreVInterface(rocUID, theXDAQContextConfigTree, theConfigurationPath), gr(false)
2424
{
2525
INIT_MF("." /*directory used is USER_DATA/LOG/.*/);
2626

@@ -90,9 +90,12 @@ ROCCosmicRayVetoInterface::ROCCosmicRayVetoInterface(
9090
"Configure ROC",
9191
static_cast<FEVInterface::frontEndMacroFunction_t>(
9292
&ROCCosmicRayVetoInterface::RocConfigure),
93-
std::vector<std::string>{"send GR packages (Default: false)",
94-
"# of counter packages (Default: 0)",
95-
"uB offset (if not GR) (Default: 0xa)"},
93+
std::vector<std::string>{
94+
"send GR packages (Default: false)",
95+
"# of counter packages (Default: 0)",
96+
"uB offset (if not GR) (Default: 0xa)",
97+
"ROC timeout, units of 6.25ns, off: 0xffff (Default: off)",
98+
},
9699
std::vector<std::string>{},
97100
1); // requiredUserPermissions
98101

@@ -357,7 +360,7 @@ ROCCosmicRayVetoInterface::ROCCosmicRayVetoInterface(
357360
"FEB II Configure",
358361
static_cast<FEVInterface::frontEndMacroFunction_t>(
359362
&ROCCosmicRayVetoInterface::FebIIConfigure),
360-
std::vector<std::string>{"port (Default: -1, current active)",
363+
std::vector<std::string>{"port (Default: -1: current active, 0: all)",
361364
"bias (Default: 0xaaf)",
362365
"skip bias (Default: false)",
363366
"threshold (Default: 0x50)",
@@ -457,7 +460,7 @@ void ROCCosmicRayVetoInterface::configure(void)
457460
try
458461
{
459462
__COUT_INFO__ << "configure CRV ROC";
460-
bool gr = false;
463+
// bool gr = false;
461464
try
462465
{
463466
auto rocConfigs = getSelfNode()
@@ -482,7 +485,7 @@ try
482485
"mode not set, default to "
483486
<< gr << __E__;
484487
}
485-
RocConfigure(gr);
488+
RocConfigure(gr, 0, 0x0, 0xffff);
486489

487490
// ================================ FEB part ================================
488491

@@ -527,7 +530,8 @@ void ROCCosmicRayVetoInterface::resume(void) {}
527530
//==============================================================================
528531
void ROCCosmicRayVetoInterface::start(std::string)
529532
{ // runNumber)
530-
ResetRxBuffers();
533+
// ResetRxBuffers();
534+
RocConfigure(gr, 0, 0x0, 0xffff);
531535
// take pedestrals
532536
// this->writeRegister(FEB::AllFEB|FEB::AllFPGA|FEB::CSRBroadCast, 0x100);
533537
// TLOG(TLVL_Start) << "Taking pedestrals" << __E__;
@@ -788,7 +792,10 @@ void ROCCosmicRayVetoInterface::FebConfigure(bool useOtsConfig)
788792
}
789793
}
790794

791-
void ROCCosmicRayVetoInterface::RocConfigure(bool gr, uint16_t grn, uint16_t uBoffset)
795+
void ROCCosmicRayVetoInterface::RocConfigure(bool gr,
796+
uint16_t grn,
797+
uint16_t uBoffset,
798+
uint16_t timeout)
792799
{
793800
TLOG(TLVL_ROCConfig) << "RocConfigure Start " << __E__;
794801

@@ -809,23 +816,45 @@ void ROCCosmicRayVetoInterface::RocConfigure(bool gr, uint16_t grn, uint16_t uBo
809816

810817
this->writeRegister(ROC::Clk80MHz, 0x1); // enable the 80MHz clock alignment
811818

819+
// Reset procedure
820+
// Reset FM Rx: bit 0
821+
// Reset DDR write: bit 5 from 0 to 1
822+
// Reset DDR read (Init): bit 8
823+
// :::::::::::::::;
824+
// 0x009, 0x0A8, 0x1A8
825+
812826
// Set CSR of data-FPGAs
827+
// bit 0: Reset FM Rx
813828
// bit 3: FM Rx Enable
814829
// bit 5: DDR Write Sequencer Enable
815830
// bit 7: DDR read sequencer Enable
816-
this->writeRegister(ROC::Data_Broadcast | ROC::Data_CRC, 0xA8); //
831+
// bit 8: DDR Init (reset read pointer)
832+
833+
// this->writeRegister(ROC::Data_Broadcast | ROC::Data_CRC, 0x009);
834+
// ResetRxBuffers();
835+
this->writeRegister(ROC::Data_Broadcast | ROC::Data_CRC, 0x009);
836+
// usleep(100);
837+
this->writeRegister(ROC::Data_Broadcast | ROC::Data_CRC, 0x0A8);
838+
// usleep(100);
839+
this->writeRegister(ROC::Data_Broadcast | ROC::Data_CRC, 0x1A8);
840+
// usleep(100);
841+
this->writeRegister(ROC::GTP_CRC, 0x1);
817842

818-
// Reset input buffers
819-
ResetRxBuffers();
843+
// this->writeRegister(ROC::Data_Broadcast | ROC::Data_CRC, 0x08); //
820844

845+
// Reset input buffers
846+
// ResetRxBuffers();
847+
// usleep(100);
848+
//
821849
// Reset DDR on Data FPGAs
822-
for(int i = 0; i < 3; ++i)
823-
{
824-
this->writeRegister(ROC::Data[i] | ROC::Data_DDR_WriteHigh, 0x0);
825-
this->writeRegister(ROC::Data[i] | ROC::Data_DDR_WriteLow, 0x0);
826-
this->writeRegister(ROC::Data[i] | ROC::Data_DDR_ReadHigh, 0x0);
827-
this->writeRegister(ROC::Data[i] | ROC::Data_DDR_ReadLow, 0x0);
828-
}
850+
// for(int i = 0; i < 3; ++i)
851+
//{
852+
// this->writeRegister(ROC::Data[i] | ROC::Data_DDR_WriteHigh, 0x0);
853+
// this->writeRegister(ROC::Data[i] | ROC::Data_DDR_WriteLow, 0x0);
854+
// this->writeRegister(ROC::Data[i] | ROC::Data_DDR_ReadHigh, 0x0);
855+
// this->writeRegister(ROC::Data[i] | ROC::Data_DDR_ReadLow, 0x0);
856+
//}
857+
// this->writeRegister(ROC::Data_Broadcast | ROC::Data_CRC, 0xA8); //
829858

830859
// Set TRIG 1
831860
this->writeRegister(ROC::TRIG, 0x1);
@@ -839,17 +868,20 @@ void ROCCosmicRayVetoInterface::RocConfigure(bool gr, uint16_t grn, uint16_t uBo
839868
// this->writeRegister(ROC::sendGR, 0x2);///
840869

841870
// Disable send of active FEBs
842-
this->writeRegister(ROC::Data[0] | ROC::Data_LinkCtrl, 0x0);
871+
// this->writeRegister(ROC::Data[0] | ROC::Data_LinkCtrl, 0x0);
843872
this->writeRegister(ROC::uBOffset, 0x0);
844873
}
845874
else
846875
{
847876
this->writeRegister(ROC::sendGR, 0x0);
848877

849878
// Enable send of active FEBs
850-
this->writeRegister(ROC::Data[0] | ROC::Data_LinkCtrl, 0x0);
879+
// this->writeRegister(ROC::Data[0] | ROC::Data_LinkCtrl, 0x0);
851880
this->writeRegister(ROC::uBOffset, uBoffset);
852881
}
882+
883+
// 0xffff means disable timeout
884+
this->writeRegister(ROC::DRTimeout, timeout);
853885
}
854886

855887
void ROCCosmicRayVetoInterface::Configure(__ARGS__)
@@ -904,7 +936,9 @@ void ROCCosmicRayVetoInterface::RocConfigure(__ARGS__)
904936
uint16_t grn = __GET_ARG_IN__("# of counter packages (Default: 0)", uint16_t, 0);
905937
uint16_t uBoffset =
906938
__GET_ARG_IN__("uB offset (if not GR) (Default: 0xa)", uint16_t, 0xa);
907-
RocConfigure(gr, grn, uBoffset);
939+
uint16_t rocTimeout = __GET_ARG_IN__(
940+
"ROC timeout, units of 6.25ns, off: 0xffff (Default: off)", uint16_t, 0xffff);
941+
RocConfigure(gr, grn, uBoffset, rocTimeout);
908942
}
909943

910944
void ROCCosmicRayVetoInterface::FebConfigure(__ARGS__)
@@ -1594,7 +1628,7 @@ void ROCCosmicRayVetoInterface::SetActivePort(uint16_t port, bool check)
15941628
auto startTime = std::chrono::high_resolution_clock::now();
15951629
while(std::chrono::duration_cast<std::chrono::milliseconds>(
15961630
std::chrono::high_resolution_clock::now() - startTime)
1597-
.count() < 1000)
1631+
.count() < 3000)
15981632
{
15991633
try
16001634
{
@@ -1613,7 +1647,7 @@ void ROCCosmicRayVetoInterface::SetActivePort(uint16_t port, bool check)
16131647
}
16141648
catch(...)
16151649
{
1616-
usleep(5000); // 5ms before retry
1650+
usleep(5000); // 50ms before retry
16171651
}
16181652
}
16191653
}
@@ -1995,11 +2029,14 @@ void ROCCosmicRayVetoInterface::FebIITrigBaselines(__ARGS__)
19952029
__SET_ARG_OUT__("response", ostr.str());
19962030
}
19972031

1998-
void ROCCosmicRayVetoInterface::ResetPLL(int sleep_ms)
2032+
void ROCCosmicRayVetoInterface::ResetPLL(int sleep_ms, bool allPorts)
19992033
{
2000-
this->writeRegister(FEBII::EWTFakeMode, 0x1); // fake mode, Ph_det off
2034+
uint16_t PORT_ = ROC::FEB;
2035+
if(allPorts)
2036+
PORT_ = ROC::FEB_Broadcast;
2037+
this->writeRegister(PORT_ | FEBII::EWTFakeMode, 0x1); // fake mode, Ph_det off
20012038
usleep(sleep_ms * 1000);
2002-
this->writeRegister(FEBII::EWTFakeMode,
2039+
this->writeRegister(PORT_ | FEBII::EWTFakeMode,
20032040
0x0); // back to extenral, Ph_det enabled again
20042041
usleep(sleep_ms * 1000);
20052042
}
@@ -2101,8 +2138,8 @@ void ROCCosmicRayVetoInterface::SetInputMask(__ARGS__)
21012138

21022139
void ROCCosmicRayVetoInterface::FebIIConfigure(__ARGS__)
21032140
{
2104-
int port = __GET_ARG_IN__("port (Default: -1, current active)", int, -1);
2105-
uint16_t bias = __GET_ARG_IN__("bias (Default: 0xaaf)", uint16_t, 0xaaf);
2141+
int port = __GET_ARG_IN__("port (Default: -1: current active, 0: all)", int, -1);
2142+
uint16_t bias = __GET_ARG_IN__("bias (Default: 0xaaf)", uint16_t, 0xaaf);
21062143
bool skip_bias = __GET_ARG_IN__("skip bias (Default: false)", bool, false);
21072144
uint16_t threshold = __GET_ARG_IN__("threshold (Default: 0x50)", uint16_t, 0x50);
21082145
bool update_baseline = __GET_ARG_IN__("update baseline (Default: true)", bool, true);
@@ -2112,38 +2149,26 @@ void ROCCosmicRayVetoInterface::FebIIConfigure(__ARGS__)
21122149
__GET_ARG_IN__("offSpillGateEnd (Default: 15000, 6.25ns)", uint16_t, 15000);
21132150
bool pll_reset = __GET_ARG_IN__("pll reset (Default: true)", bool, true);
21142151

2115-
if(port > 0)
2116-
SetActivePort(port);
21172152
std::stringstream ostr;
2118-
2119-
// Reset PLL
2120-
if(pll_reset)
2153+
ostr << std::endl;
2154+
if(port > 0)
21212155
{
2122-
ostr << "Resetting PLL (wait 1s)" << std::endl;
2123-
ResetPLL(1000);
2156+
ostr << "Selecting port " << port << std::endl;
2157+
SetActivePort(port);
21242158
}
21252159

2126-
// forcer AFE to realign
2127-
uint16_t status = Realign(1000);
2128-
ostr << "Forcing AFE realignment: " << ((status & 0x1) ? "inverted" : "default")
2129-
<< ", " << ((status & 0x2) ? "inverted" : "default") << ", "
2130-
<< ((status & 0x4) ? "inverted" : "default") << ", "
2131-
<< ((status & 0x8) ? "inverted" : "default") << std::endl;
2132-
2133-
// set port
2134-
if(port == -1)
2160+
uint16_t PORT_ = ROC::FEB;
2161+
if(port == 0)
21352162
{
2136-
// int16_t aport = GetActivePorts();
2137-
// for(unsigned int fpga = 0; fpga < 4; fpga++) {
2138-
// this->writeRegister(FEBII::FPGA[fpga] | FEBII::Port, aport);
2139-
// }
2163+
PORT_ = PORT_ | ROC::FEB_Broadcast;
2164+
ostr << "Broadcast to all ports" << std::endl;
21402165
}
2141-
else
2166+
2167+
// Reset PLL
2168+
if(pll_reset)
21422169
{
2143-
for(unsigned int fpga = 0; fpga < 4; fpga++)
2144-
{ // TODO, when avaiable use 0x329
2145-
this->writeRegister(FEBII::FPGA[fpga] | FEBII::Port, port);
2146-
}
2170+
ostr << "Resetting PLL (wait 1s)" << std::endl;
2171+
ResetPLL(1000, port == 0);
21472172
}
21482173

21492174
// bias
@@ -2155,13 +2180,61 @@ void ROCCosmicRayVetoInterface::FebIIConfigure(__ARGS__)
21552180
{
21562181
for(uint16_t idx = 0; idx < 2; ++idx)
21572182
{
2158-
this->writeRegister(FEBII::FPGA[fpga] | (FEBII::BiasBase + (idx & 0x1)),
2159-
bias);
2183+
this->writeRegister(
2184+
PORT_ | FEBII::FPGA[fpga] | (FEBII::BiasBase + (idx & 0x1)), bias);
21602185
sleep(5);
21612186
}
21622187
}
21632188
}
21642189

2190+
// things that can not be done as broadcast
2191+
uint32_t active = GetActivePorts();
2192+
for(uint16_t p = 1; p <= 24; p++)
2193+
{
2194+
if((port > 0) & (p != port))
2195+
continue;
2196+
2197+
if(port != -1)
2198+
{ // not the active port, then set it
2199+
if(active & (0x00000001 << (p - 1)))
2200+
{
2201+
SetActivePort(p);
2202+
// set port
2203+
this->writeRegister(FEBII::PortAll, p);
2204+
}
2205+
}
2206+
2207+
// forcer AFE to realign
2208+
2209+
/*
2210+
uint16_t status = Realign(1000);
2211+
ostr << "Forcing AFE realignment: " << ((status & 0x1) ? "inverted" : "default")
2212+
<< ", " << ((status & 0x2) ? "inverted" : "default") << ", "
2213+
<< ((status & 0x4) ? "inverted" : "default") << ", "
2214+
<< ((status & 0x8) ? "inverted" : "default") << std::endl;
2215+
*/
2216+
2217+
// set port
2218+
// if(port != -1) {
2219+
// this->writeRegister(FEBII::PortAll, p);
2220+
//}
2221+
2222+
// if(port == -1){
2223+
// // int16_t aport = GetActivePorts();
2224+
// // for(unsigned int fpga = 0; fpga < 4; fpga++) {
2225+
// // this->writeRegister(FEBII::FPGA[fpga] | FEBII::Port, aport);
2226+
// // }
2227+
// } else {
2228+
// for(unsigned int fpga = 0; fpga < 4; fpga++) { // TODO, when avaiable use
2229+
// 0x329
2230+
// this->writeRegister(FEBII::FPGA[fpga] | FEBII::Port, p);
2231+
// }
2232+
// }
2233+
if(port != 0)
2234+
break; // only do one or the active port
2235+
}
2236+
2237+
// and back to broadcastable
21652238
// Enable channels, and thresholds, trigger baseline
21662239
ostr << "Enabling channels, and thresholds";
21672240
if(update_baseline)
@@ -2171,23 +2244,24 @@ void ROCCosmicRayVetoInterface::FebIIConfigure(__ARGS__)
21712244
{
21722245
for(uint16_t ch = 0; ch < 16; ++ch)
21732246
{
2174-
this->writeRegister(FEBII::FPGA[fpga] | (FEBII::ChannelMapBase + (ch & 0xF)),
2175-
ch);
2176-
this->writeRegister(FEBII::FPGA[fpga] | (FEBII::ThresholdBase + (ch & 0xF)),
2177-
threshold);
2247+
this->writeRegister(
2248+
PORT_ | FEBII::FPGA[fpga] | (FEBII::ChannelMapBase + (ch & 0xF)), ch);
2249+
this->writeRegister(
2250+
PORT_ | FEBII::FPGA[fpga] | (FEBII::ThresholdBase + (ch & 0xF)),
2251+
threshold);
21782252
if(update_baseline)
21792253
{
21802254
this->writeRegister(
2181-
FEBII::FPGA[fpga] | (FEBII::BaselineBase + (ch & 0xF)), 0x1);
2255+
PORT_ | FEBII::FPGA[fpga] | (FEBII::BaselineBase + (ch & 0xF)), 0x1);
21822256
}
21832257
}
21842258
}
21852259

21862260
ostr << "Setting on-spill gate end to " << onSpillGateEnd
21872261
<< "(6.25ns) and off-spill gate end to " << offSpillGateEnd << "(6.25ns)"
21882262
<< std::endl;
2189-
this->writeRegister(FEBII::GateOffOnSpill, onSpillGateEnd);
2190-
this->writeRegister(FEBII::GateOffOffSpill, offSpillGateEnd);
2263+
this->writeRegister(PORT_ | FEBII::GateOffOnSpill, onSpillGateEnd);
2264+
this->writeRegister(PORT_ | FEBII::GateOffOffSpill, offSpillGateEnd);
21912265

21922266
__SET_ARG_OUT__("response", ostr.str());
21932267
}

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