|
| 1 | +#ifndef FEBII_REGISTERS_H |
| 2 | +#define FEBII_REGISTERS_H |
| 3 | + |
| 4 | +// #include <functional> // std::bind, std::function (if needed) |
| 5 | +#include <cstdint> // uint16_t |
| 6 | + |
| 7 | +// Source: https://github.com/Mu2e/cRV_FEB2 |
| 8 | + |
| 9 | +namespace FEBII |
| 10 | +{ |
| 11 | +enum Register : uint16_t |
| 12 | +{ |
| 13 | + // FPGA registers |
| 14 | + CR = 0x1000, |
| 15 | + // bit 8 = clear DDR FIFO nearly full warning |
| 16 | + // bit 7 = clear encoded FM clock parity error |
| 17 | + // bit 6 = hard reset AFE chips |
| 18 | + // bit 5 = general soft reset for FPGA logic (does not stop clocks) |
| 19 | + // bit 2 = reset AFE front end (force front end recalibration and realignment) |
| 20 | + // bit 1 = AFE1 power down |
| 21 | + // bit 0 = AFE0 power down |
| 22 | + Status = 0x1001, |
| 23 | + FirmwareLO = 0x1002, |
| 24 | + FirmwareHI = 0x1003, |
| 25 | + OutFIFI = 0x100c, |
| 26 | + OutFIFOStatus = 0x1017, |
| 27 | + CntHI = 0x1022, |
| 28 | + CntLO = 0x1023, |
| 29 | + ThresholdGlobal = 0x1026, |
| 30 | + Port = 0x1029, |
| 31 | + UptimeHI = 0x106C, |
| 32 | + UptimeLo = 0x106D, |
| 33 | + EWT = 0x106E, |
| 34 | + EWTCount = 0x106F, |
| 35 | + ThresholdBase = 0x1070, // to 0x107F |
| 36 | + ChannelMapBase = 0x1080, // to 0x108F |
| 37 | + // implemented in uC |
| 38 | + BaselineBase = 0x1090, |
| 39 | + TrimBase = 0x10b0, // to 0x1090 |
| 40 | + LEDBias = 0x10a0, // to 0x10a3 |
| 41 | + BiasBase = 0x10a4, // to 0x10a5 |
| 42 | + VGABase = 0x10a6, // to 0x10a7 |
| 43 | + |
| 44 | + // AFE reads |
| 45 | + AFE0_base = 0x1100, |
| 46 | + AFE1_base = 0x1200, |
| 47 | + |
| 48 | + // registers that effect all FPGAs |
| 49 | + FlashGateEn = 0x1300, |
| 50 | + FlashGateOn = 0x1301, // 6.25ns, default 1 |
| 51 | + FlashGateOff = 0x1302, // 6.25ns, default 112 |
| 52 | + EWTFakeMode = 0x1303, |
| 53 | + GateOnOnSpill = 0x1305, // 6.25ns, default 16 |
| 54 | + GateOffOnSpill = 0x1306, // 6.25ns, default 255 |
| 55 | + GateOnOffSpill = 0x1307, // 6.25ns, default 16 |
| 56 | + GateOffOffSpill = 0x1308, // 6.25ns, default 1792 |
| 57 | + LEDOn = 0x1318, // 6.25ns, default |
| 58 | + |
| 59 | + // broadcast to all FEBs on ROC |
| 60 | + AllFEB = 0x3000, |
| 61 | + // uC functions |
| 62 | + Reset = 0x9001, |
| 63 | + TRIG = 0x900B, |
| 64 | + CMBENA = 0x9106 |
| 65 | +}; // end ROC_Register enum |
| 66 | + |
| 67 | +enum AFERegister : uint16_t |
| 68 | +{ |
| 69 | + // AFE registers, write only (read is a multi step process) |
| 70 | + Offset_en = 0x3, // bit 8 |
| 71 | + Offset_ch1 = 0x0D, |
| 72 | + Offset_ch2 = 0x0F, |
| 73 | + Offset_ch3 = 0x11, |
| 74 | + Offset_ch4 = 0x13, |
| 75 | + Offset_ch5 = 0x1F, |
| 76 | + Offset_ch6 = 0x1D, |
| 77 | + Offset_ch7 = 0x1B, |
| 78 | + Offset_ch8 = 0x19, |
| 79 | +}; |
| 80 | + |
| 81 | +uint16_t FPGA[] = {0x000, 0x400, 0x800, 0xC00}; |
| 82 | + |
| 83 | +} // namespace FEBII |
| 84 | + |
| 85 | +#endif // FEBII_REGISTERS_H |
0 commit comments