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Merge pull request #18 from Mu2e/scorrodi/FebII
adding first FEBII registers and functions
2 parents f72ef26 + b3b6907 commit e3b3a42

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#ifndef FEBII_REGISTERS_H
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#define FEBII_REGISTERS_H
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// #include <functional> // std::bind, std::function (if needed)
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#include <cstdint> // uint16_t
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// Source: https://github.com/Mu2e/cRV_FEB2
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namespace FEBII
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{
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enum Register : uint16_t
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{
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// FPGA registers
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CR = 0x1000,
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// bit 8 = clear DDR FIFO nearly full warning
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// bit 7 = clear encoded FM clock parity error
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// bit 6 = hard reset AFE chips
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// bit 5 = general soft reset for FPGA logic (does not stop clocks)
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// bit 2 = reset AFE front end (force front end recalibration and realignment)
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// bit 1 = AFE1 power down
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// bit 0 = AFE0 power down
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Status = 0x1001,
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FirmwareLO = 0x1002,
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FirmwareHI = 0x1003,
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OutFIFI = 0x100c,
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OutFIFOStatus = 0x1017,
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CntHI = 0x1022,
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CntLO = 0x1023,
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ThresholdGlobal = 0x1026,
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Port = 0x1029,
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UptimeHI = 0x106C,
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UptimeLo = 0x106D,
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EWT = 0x106E,
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EWTCount = 0x106F,
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ThresholdBase = 0x1070, // to 0x107F
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ChannelMapBase = 0x1080, // to 0x108F
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// implemented in uC
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BaselineBase = 0x1090,
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TrimBase = 0x10b0, // to 0x1090
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LEDBias = 0x10a0, // to 0x10a3
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BiasBase = 0x10a4, // to 0x10a5
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VGABase = 0x10a6, // to 0x10a7
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// AFE reads
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AFE0_base = 0x1100,
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AFE1_base = 0x1200,
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// registers that effect all FPGAs
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FlashGateEn = 0x1300,
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FlashGateOn = 0x1301, // 6.25ns, default 1
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FlashGateOff = 0x1302, // 6.25ns, default 112
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EWTFakeMode = 0x1303,
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GateOnOnSpill = 0x1305, // 6.25ns, default 16
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GateOffOnSpill = 0x1306, // 6.25ns, default 255
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GateOnOffSpill = 0x1307, // 6.25ns, default 16
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GateOffOffSpill = 0x1308, // 6.25ns, default 1792
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LEDOn = 0x1318, // 6.25ns, default
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// broadcast to all FEBs on ROC
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AllFEB = 0x3000,
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// uC functions
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Reset = 0x9001,
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TRIG = 0x900B,
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CMBENA = 0x9106
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}; // end ROC_Register enum
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enum AFERegister : uint16_t
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{
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// AFE registers, write only (read is a multi step process)
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Offset_en = 0x3, // bit 8
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Offset_ch1 = 0x0D,
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Offset_ch2 = 0x0F,
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Offset_ch3 = 0x11,
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Offset_ch4 = 0x13,
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Offset_ch5 = 0x1F,
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Offset_ch6 = 0x1D,
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Offset_ch7 = 0x1B,
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Offset_ch8 = 0x19,
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};
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uint16_t FPGA[] = {0x000, 0x400, 0x800, 0xC00};
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} // namespace FEBII
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#endif // FEBII_REGISTERS_H

otsdaq-mu2e-crv/FEInterfaces/ROCCosmicRayVetoInterface.h

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void FebConfigure(bool useOtsConfig = true);
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void ResetRxBuffers();
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void SetMarkerSync(bool enable=true);
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int16_t Realign(int sleep_uc = 1000);
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void ResetPLL(int sleep_us = 1000);
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uint16_t ReadAFE(uint16_t fpga, uint16_t afe_no, uint16_t reg);
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// CRV FEB specific functions
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//void FebTakePedestral();
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void PWRRST (__ARGS__);
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void GetHistograms (__ARGS__);
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void RegDump (__ARGS__);
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void FebIIConfigure (__ARGS__);
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void FebIIAlign (__ARGS__);
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void FebIISetThreshold (__ARGS__);
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void FebIISetBias (__ARGS__);
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void FebIISetBiasTrim (__ARGS__);
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void FebIISetGateOnSpill (__ARGS__);
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void FebIISetGateOffSpill (__ARGS__);
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void FebIIGetStatus (__ARGS__);
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void FebIISetChannel (__ARGS__);
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void FebIISetAFEOffset (__ARGS__);
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void FebIIGetBaselines (__ARGS__);
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void FebIITrigBaselines (__ARGS__);
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void SetInputMask (__ARGS__);
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// clang-format on
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};
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