msp430fr413x_CS_05.c

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 *                       MSP430 CODE EXAMPLE DISCLAIMER
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 * MSP430 code examples are self-contained low-level programs that typically
 * demonstrate a single peripheral function or device feature in a highly
 * concise manner. For this the code may rely on the device's power-on default
 * register values and settings such as the clock configuration and care must
 * be taken when combining code from several examples to avoid potential side
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 * for an API functional library-approach to peripheral configuration.
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//******************************************************************************
//  MSP430FR413x Demo - Configure MCLK for 16MHz operation, and XT1 sourcing
//                                     FLLREF and ACLK. 
//
//  Description: Configure MCLK for 16MHz. FLL reference clock is XT1. At this 
//                    speed, the FRAM requires wait states. 
//                    ACLK = XT1 ~32768Hz, SMCLK = MCLK = 16MHz. 
//                    Toggle LED to indicate that the program is running.
//
//           MSP430FR4133
//         ---------------
//        |               |
//        |            XIN|--
//     /|\|               |  ~32768Hz
//      | |           XOUT|--
//      --|RST            |
//        |               |
//        |          P1.0 |--> LED
//        |          P1.4 |---> MCLK = 16MHz
//        |          P8.0 |---> SMCLK = 16MHz
//        |          P8.1 |---> ACLK = 32768Hz
//
//
//   Kathryn Adamsky
//   Texas Instruments Inc.
//   June 2016
//   Built with IAR Embedded Workbench v6.10.2 & Code Composer Studio v6.1.3
//******************************************************************************
#include <msp430.h>

int main(void)
{
    WDTCTL = WDTPW | WDTHOLD;                    // Stop watchdog timer

    // Configure one FRAM waitstate as required by the device datasheet for MCLK
    // operation beyond 8MHz _before_ configuring the clock system.
    FRCTL0 = FRCTLPW | NWAITS_1;

    P4SEL0 |= BIT1 | BIT2;                       // set XT1 pin as second function
    do
    {
        CSCTL7 &= ~(XT1OFFG | DCOFFG);           // Clear XT1 and DCO fault flag
        SFRIFG1 &= ~OFIFG;
    } while (SFRIFG1 & OFIFG);                   // Test oscillator fault flag

    __bis_SR_register(SCG0);                     // disable FLL
    CSCTL3 |= SELREF__XT1CLK;                    // Set XT1 as FLL reference source
    CSCTL0 = 0;                                  // clear DCO and MOD registers
    CSCTL1 &= ~(DCORSEL_7);                      // Clear DCO frequency select bits first
    CSCTL1 |= DCORSEL_5;                         // Set DCO = 16MHz
    CSCTL2 = FLLD_0 + 487;                       // DCOCLKDIV = 16MHz
    __delay_cycles(3);  
    __bic_SR_register(SCG0);                     // enable FLL
    while(CSCTL7 & (FLLUNLOCK0 | FLLUNLOCK1));   // FLL locked

    CSCTL4 = SELMS__DCOCLKDIV | SELA__XT1CLK;    // set XT1 (~32768Hz) as ACLK source, ACLK = 32768Hz
                                                 // default DCOCLKDIV as MCLK and SMCLK source

    P1DIR |= BIT0 + BIT4;                        // set MCLK and LED pin as output
    P1SEL0 |= BIT4;                              // set MCLK pin as second function
    P8DIR |= BIT0 | BIT1;                        // set ACLK and SMCLK pin as output
    P8SEL0 |= BIT0 | BIT1;                       // set ACLK and SMCLK pin as second function

    PM5CTL0 &= ~LOCKLPM5;                        // Disable the GPIO power-on default high-impedance mode
                                                 // to activate previously configured port settings

    while(1)
    {
        P1OUT ^= BIT0;                           // Toggle P1.0 using exclusive-OR
        __delay_cycles(8000000);                 // Delay for 80000*(1/MCLK)=0.5s
    }
}