msp430fr413x_LPM3_02.c

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 *                       MSP430 CODE EXAMPLE DISCLAIMER
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 * demonstrate a single peripheral function or device feature in a highly
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 * register values and settings such as the clock configuration and care must
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 * for an API functional library-approach to peripheral configuration.
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//******************************************************************************
//  MSP430FR413x Demo - LPM3 entry with MCLK 16MHz
//
//  Description: When MCLK is 16MHz, and if the temperature changes signicantly 
//                    for entering LPM3 and exiting from LPM3, the MCLK frequency at 
//                    wake-up may be significantly different from when the LPM3 is 
//                    entered, and may be out of the specified operation range. To avoid
//                    this, the MCLK can be set to be divided from DCOCLKDIV. 
// 
//           MSP430FR4133
//         ---------------
//     /|\|               |
//      | |               |
//      --|RST       P1.0 |---> LED
//        |               |

//
//
//  Kathryn Adamsky
//  Texas Instruments Inc.
//  June 2016 (Updated) | June 2014 (Created)
//  Built with IAR Embedded Workbench v6.10.2 & Code Composer Studio v5.5
//******************************************************************************
#include <msp430.h>

void Init_GPIO(void);

int main(void)
{
    WDTCTL = WDTPW | WDTHOLD;                                              // Stop watchdog timer
    
    // Configure GPIO
    Init_GPIO();
    P1OUT &= ~BIT0;                                                        // Clear P1.0 output latch for a defined power-on state
    P1DIR |= BIT0;                                                         // Set P1.0 to output direction
    
    // Disable the GPIO power-on default high-impedance mode
    // to activate previously configured port settings
    PM5CTL0 &= ~LOCKLPM5;

    __bis_SR_register(SCG0);                                               // disable FLL
    CSCTL3 |= SELREF__REFOCLK;                                             // Set REFO as FLL reference source
    CSCTL0 = 0;                                                            // clear DCO and MOD registers
    CSCTL1 &= ~(DCORSEL_7);                                                // Clear DCO frequency select bits first
    CSCTL1 |= DCORSEL_5;                                                   // Set DCO = 16MHz
    CSCTL2 = FLLD_0 + 487;                                                 // DCOCLKDIV = 16MHz
    __delay_cycles(3);   
    __bic_SR_register(SCG0);                                               // enable FLL
    while(CSCTL7 & (FLLUNLOCK0 | FLLUNLOCK1));                             // FLL locked
    FRCTL0 = FRCTLPW | NWAITS0;                                            // Set number of FRAM waitstates to 0
    CSCTL4 = SELMS__DCOCLKDIV | SELA__REFOCLK;                             // set default REFO(~32768Hz) as ACLK source, ACLK = 32768Hz
                                                                           // default DCOCLKDIV as MCLK and SMCLK source
   
    // Configure RTC
    RTCMOD = 10-1;                                                         // Interrupt and reset happen every 10*1000*(1/10KHz) = ~1S
    RTCCTL |= RTCSS__VLOCLK | RTCSR |RTCPS__1000;                          
    RTCCTL |= RTCIE;
   
    while(1)
    {  
        CSCTL5 |= DIVM_1;                                                  // MCLK = 0.5* DCOCLKDIV = 8MHz - only for case of temperature changes significantly for LPM3 entry and LPM3 exit

        P1OUT ^= BIT0;
        
        __bis_SR_register(LPM3_bits | GIE);                                // Enter LPM3, Stop all clocks
        __no_operation();                                                  // For debugger
    }
}

// RTC interrupt service routine
#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector=RTC_VECTOR
__interrupt void RTC_ISR(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(RTC_VECTOR))) RTC_ISR (void)
#else
#error Compiler not supported!
#endif
{
    // Configure the CS
    __bic_SR_register(SCG0);                                               // enable FLL
    while(CSCTL7 & (FLLUNLOCK0 | FLLUNLOCK1));                             // FLL locked
  
    CSCTL5 &= DIVM_1;                                                      // MCLK = DCOCLKDIV = 16MHz - only for case of temperature changes significantly for LPM3 entry and LPM3 exit

    switch(__even_in_range(RTCIV,RTCIV_RTCIF))
    {
        case RTCIV_NONE :  break;                                          // No interrupt
        case RTCIV_RTCIF:  __bic_SR_register_on_exit(LPM3_bits);           // RTC Overflow
                                                                           // Exit LPM3 on reti
                           break;
        default: break;
    }
}

void Init_GPIO()
{
    P1DIR = 0xFF; P2DIR = 0xFF; P3DIR = 0xFF; P4DIR = 0xFF; 
    P5DIR = 0xFF; P6DIR = 0xFF; P7DIR = 0xFF; P8DIR = 0xFF; 
    P1REN = 0xFF; P2REN = 0xFF; P3REN = 0xFF; P4REN = 0xFF;
    P5REN = 0xFF; P6REN = 0xFF; P7REN = 0xFF; P8REN = 0xFF;
    P1OUT = 0x00; P2OUT = 0x00; P3OUT = 0x00; P4OUT = 0x00; 
    P5OUT = 0x00; P6OUT = 0x00; P7OUT = 0x00; P8OUT = 0x00;
}