msp430fr413x_WDT_06.c

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//******************************************************************************
//  MSP430FR413x Demo - WDT, Failsafe Clock, WDT mode, 32kHz ACLK
//
//  Description; Allow WDT in watchdog to timeout sourced by ACLK. LPM3 is
//  entered, this example will demonstrate WDT feature by automatically
//  re-enabling WDT clock source as DCO if external XTAL fails. This can be
//  seen as a continued, though faster as clocked by DCO, watchdog timeout
//  which will toggle on P1.0 in main function.
//  ACLK = REFO = 32kHz, MCLK = SMCLK = default DCO ~1MHz.
//
//                MSP430FR4133
//             -----------------
//         /|\|                 |
//          | |                 |
//          --|RST              |
//            |                 |
//            |             P1.0|-->LED
//
// Cen Fang
// Texas Instruments Inc.
// August 2013
// Built with IAR Embedded Workbench v5.60 & Code Composer Studio v5.5
//******************************************************************************
#include <msp430.h>

int main(void)
{
    // Selects the ACLK source to REFO (internal 32kHz clock source) as default
    WDTCTL = WDT_ARST_1000;                 // Set Watchdog Timer timeout 1s
    P1DIR |= BIT0;                          // Set P1.0 to output direction

    // Disable the GPIO power-on default high-impedance mode
    // to activate previously configured port settings
    PM5CTL0 &= ~LOCKLPM5;

    P1OUT ^= BIT0;                          // Toggle P1.0
    __bis_SR_register(LPM3_bits | GIE);     // Enter LPM3
}