build_circuit --frame 1 gives segmetation fault

[sitetree]

I have a segmentation fault.
Hot to debug?

==========================================================================

Kernel: Linux

Platform: x86_64

Memory: 15806.3 MB

atpg_top.script 1> read_lib mod_nangate45.mdt

Reading technology library ...

Finished reading library `mod_nangate45.mdt' 0.012361 s 9.35938 MB

atpg_top.script 2> report_lib

library information

number of models: 137

models: seq3 seq3_1 seq3_2 seq3_3 seq3_4 seq3_5 udp_dff udp_mux AND2_X1 AND2_X2 AND2_X4 AND3_X1 AND3_X2 AND3_X4 AND4_X1 AND4_X2 AND4_X4 ANTENNA_X1 AOI211_X1 AOI211_X2 AOI211_X4 AOI21_X1 AOI21_X2 AOI21_X4 AOI221_X1 AOI221_X2 AOI221_X4 AOI222_X1 AOI222_X2 AOI222_X4 AOI22_X1 AOI22_X2 AOI22_X4 BUF_X1 BUF_X16 BUF_X2 BUF_X3 BUF_X32 BUF_X4 BUF_X8 CLKBUF_X1 CLKBUF_X2 CLKBUF_X3 CLKGATETST_X1 CLKGATETST_X2 CLKGATETST_X4 CLKGATETST_X8 CLKGATE_X1 CLKGATE_X2 CLKGATE_X4 CLKGATE_X8 DFFRS_X1 DFFRS_X2 DFFR_X1 DFFR_X2 DFFS_X1 DFFS_X2 DFF_X1 DFF_X2 DLH_X1 DLH_X2 DLL_X1 DLL_X2 FA_X1 HA_X1 INV_X1 INV_X16 INV_X2 INV_X32 INV_X4 INV_X8 LOGIC0_X1 LOGIC1_X1 MUX2_X1 MUX2_X2 NAND2_X1 NAND2_X2 NAND2_X4 NAND3_X1 NAND3_X2 NAND3_X4 NAND4_X1 NAND4_X2 NAND4_X4 NOR2_X1 NOR2_X2 NOR2_X4 NOR3_X1 NOR3_X2 NOR3_X4 NOR4_X1 NOR4_X2 NOR4_X4 OAI211_X1 OAI211_X2 OAI211_X4 OAI21_X1 OAI21_X2 OAI21_X4 OAI221_X1 OAI221_X2 OAI221_X4 OAI222_X1 OAI222_X2 OAI222_X4 OAI22_X1 OAI22_X2 OAI22_X4 OAI33_X1 OR2_X1 OR2_X2 OR2_X4 OR3_X1 OR3_X2 OR3_X4 OR4_X1 OR4_X2 OR4_X4 SDFFRS_X1 SDFFRS_X2 SDFFR_X1 SDFFR_X2 SDFFS_X1 SDFFS_X2 SDFF_X1 SDFF_X2 TBUF_X1 TBUF_X16 TBUF_X2 TBUF_X4 TBUF_X8 TINV_X1 TLAT_X1 XNOR2_X1 XNOR2_X2 XOR2_X1 XOR2_X2

atpg_top.script 3> read_netlist top_synth.v --verbose

Reading netlist ...

Finished reading netlist `top_synth.v' 0.00134 s 9.48828 MB

atpg_top.script 4> report_netlist

netlist information

number of modules: 1

modules: top

current module: top

number of ports: 29

number of cells: 29

number of nets: 49

atpg_top.script 5> build_circuit --frame 1

Building circuit ...

Segmentation fault (core dumped)

Script:
read_lib mod_nangate45.mdt
report_lib
read_netlist top_synth.v --verbose
report_netlist
build_circuit --frame 1
report_circuit
set_fault_type saf
add_fault --all
set_static_compression on
set_dynamic_compression on
set_X-Fill on
run_atpg
report_statistics > top.rpt
write_pattern top.pat
write_to_STIL top.stil
exit

Netlist:
/* Generated by Yosys 0.33 (git sha1 2584903a060) */

module top(HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7, SW15, SW14, SW13, SW12, SW11, SW10, SW9, SW8, SW7, SW6, SW5, SW4, SW3
, SW2, SW1, SW0, test_se, test_si, tstclk, test_so, test_so_n);
wire 00;
wire 01;
wire 02;
wire 03;
wire 04;
wire 05;
wire 06;
wire 07;
wire 08;
wire 09;
wire 10;
wire 11;
wire 12;
wire 13;
wire 14;
wire 15;
wire 16;
wire 17;
wire 18;
wire 19;
output HEX0;
wire HEX0;
output HEX1;
wire HEX1;
output HEX2;
wire HEX2;
output HEX3;
wire HEX3;
output HEX4;
wire HEX4;
output HEX5;
wire HEX5;
output HEX6;
wire HEX6;
output HEX7;
wire HEX7;
input SW0;
wire SW0;
input SW1;
wire SW1;
input SW10;
wire SW10;
input SW11;
wire SW11;
input SW12;
wire SW12;
input SW13;
wire SW13;
input SW14;
wire SW14;
input SW15;
wire SW15;
input SW2;
wire SW2;
input SW3;
wire SW3;
input SW4;
wire SW4;
input SW5;
wire SW5;
input SW6;
wire SW6;
input SW7;
wire SW7;
input SW8;
wire SW8;
input SW9;
wire SW9;
input test_se;
wire test_se;
input test_si;
wire test_si;
output test_so;
wire test_so;
output test_so_n;
wire test_so_n;
input tstclk;
wire tstclk;
INV_X1 20 (
.A(SW13),
.ZN(01)
);
INV_X1 21 (
.A(SW12),
.ZN(02)
);
INV_X1 22 (
.A(SW0),
.ZN(03)
);
INV_X1 23 (
.A(SW8),
.ZN(04)
);
INV_X1 24 (
.A(SW5),
.ZN(05)
);
INV_X1 25 (
.A(SW11),
.ZN(06)
);
NAND2_X1 26 (
.A1(01),
.A2(SW12),
.ZN(07)
);
NAND3_X1 27 (
.A1(01),
.A2(02),
.A3(SW14),
.ZN(08)
);
OAI21_X1 28 (
.A(08),
.B1(07),
.B2(SW14),
.ZN(09)
);
AOI21_X1 29 (
.A(SW14),
.B1(SW12),
.B2(SW13),
.ZN(10)
);
AOI21_X1 30 (
.A(10),
.B1(07),
.B2(SW14),
.ZN(11)
);
MUX2_X1 31 (
.A(09),
.B(11),
.S(SW9),
.Z(HEX4)
);
MUX2_X1 32 (
.A(09),
.B(11),
.S(SW10),
.Z(HEX5)
);
AND3_X1 33 (
.A1(03),
.A2(SW1),
.A3(SW6),
.ZN(HEX1)
);
MUX2_X1 34 (
.A(test_si),
.B(HEX1),
.S(test_se),
.Z(00)
);
MUX2_X1 35 (
.A(09),
.B(11),
.S(SW8),
.Z(HEX3)
);
MUX2_X1 36 (
.A(09),
.B(11),
.S(SW7),
.Z(HEX2)
);
NAND2_X1 37 (
.A1(SW4),
.A2(05),
.ZN(12)
);
OR2_X1 38 (
.A1(SW4),
.A2(05),
.ZN(13)
);
AOI21_X1 39 (
.A(SW3),
.B1(12),
.B2(13),
.ZN(14)
);
AOI21_X1 40 (
.A(SW2),
.B1(SW4),
.B2(05),
.ZN(15)
);
AOI221_X1 41 (
.A(15),
.B1(13),
.B2(SW3),
.C1(SW2),
.C2(14),
.ZN(HEX0)
);
MUX2_X1 42 (
.A(09),
.B(11),
.S(SW15),
.Z(HEX7)
);
NAND2_X1 43 (
.A1(SW10),
.A2(06),
.ZN(16)
);
OR2_X1 44 (
.A1(SW10),
.A2(06),
.ZN(17)
);
AOI211_X1 45 (
.A(SW9),
.B(04),
.C1(16),
.C2(17),
.ZN(18)
);
AOI21_X1 46 (
.A(SW8),
.B1(06),
.B2(SW10),
.ZN(19)
);
AOI211_X1 47 (
.A(18),
.B(19),
.C1(SW9),
.C2(17),
.ZN(HEX6)
);
DFF_X1 48 (
.CK(tstclk),
.D(00),
.Q(test_so),
.QN(test_so_n)
);
endmodule