update hashPC hash function to prevent conflict due to address line offset

Author: cwpeng0511

src/gpgpu-sim/gpu-cache.cc

@@ -2209,8 +2209,9 @@ enum cache_request_status data_cache::rd_hit_base_l1d(
   //   l1d_prediction_table[mf->get_pc()%256]--;
   //   //fprintf(stdout,"HIT Time: %d PC: %d Value: %d\n", time, storedhashedPC, l1d_prediction_table[storedhashedPC]);
   // }
-  printf("CWPENG: PC:%d hit, update table[%d] to %d, ptr:%p\n", mf->get_pc()%256, storedhashedPC, l1d_prediction_table[storedhashedPC], l1d_prediction_table) ;
-  m_tag_array->set_hashed_pc_from_tag(addr, mf, (uint8_t) mf->get_pc());  //cwpeng
+  uint8_t hashed_pc = l1_cache::pc2hashed_pc(mf->get_pc()) ;
+  printf("CWPENG: PC:%d hit, update table[%d] to %d, ptr:%p\n", hashed_pc, storedhashedPC, l1d_prediction_table[storedhashedPC], l1d_prediction_table) ;
+  m_tag_array->set_hashed_pc_from_tag(addr, mf, hashed_pc);  //cwpeng
 
   m_tag_array->access(block_addr, time, cache_index, mf);
   // Atomics treated as global read/write requests - Perform read, mark line as
@@ -2285,7 +2286,7 @@ enum cache_request_status data_cache::rd_miss_base_l1d(
   bool isBypassed = false;
   int threshold = 8; // From SDBP paper
   //fprintf(stdout,"AISH, %s, %d\n",__func__, __LINE__);
-  if(l1d_prediction_table[mf->get_pc() % 256] >= threshold){
+  if(l1d_prediction_table[l1_cache::pc2hashed_pc(mf->get_pc())] >= threshold){
     isBypassed = true;
   }
 
@@ -2526,6 +2527,10 @@ enum cache_request_status l1_cache::access(new_addr_type addr, mem_fetch *mf,
   return data_cache::access(addr, mf, time, events, l1_prediction_table);
 }
 
+uint8_t l1_cache::pc2hashed_pc(new_addr_type addr){ // cwpeng PC -> 256bit hash PC translation
+  return (addr >> 2) % 256 ;
+}
+
 // The l2 cache access function calls the base data_cache access
 // implementation.  When the L2 needs to diverge from L1, L2 specific
 // changes should be made here.

src/gpgpu-sim/gpu-cache.h

@@ -1800,6 +1800,7 @@ class l1_cache : public data_cache {
                                            );
 
   uint8_t prediction_table[256] ; // cwpeng prediction table in L1 cache (4 bits each entry)
+  static uint8_t pc2hashed_pc(new_addr_type) ; // cwpeng PC -> 256bit hash PC translation
 
  protected:
   l1_cache(const char *name, cache_config &config, int core_id, int type_id,

src/gpgpu-sim/shader.cc

@@ -2869,9 +2869,9 @@ void ldst_unit::cycle() {
                                       // on load miss only
 
         bool bypassL1D = false;
-        uint8_t temp_pc = 0; //cwpeng
         address_type currPC = mf->get_pc();
-        temp_pc = (currPC == -1) ? (uint8_t) mf->get_original_mf()->get_pc() : (uint8_t) currPC;
+        address_type temp_pc = (currPC == -1) ? (uint8_t) mf->get_original_mf()->get_pc() : currPC; //cwpeng
+        uint8_t hashed_pc = l1_cache::pc2hashed_pc(temp_pc) ;
 
         if (CACHE_GLOBAL == mf->get_inst().cache_op || (m_L1D == NULL)) {
           bypassL1D = true;
@@ -2895,7 +2895,7 @@ void ldst_unit::cycle() {
         } else {
           if (m_L1D->fill_port_free()) {
             m_L1D->fill(mf, m_core->get_gpu()->gpu_sim_cycle +
-                                m_core->get_gpu()->gpu_tot_sim_cycle, m_L1D->prediction_table, temp_pc);
+                                m_core->get_gpu()->gpu_tot_sim_cycle, m_L1D->prediction_table, hashed_pc);
             m_response_fifo.pop_front();
           }
         }