[None][fix] impl fused triton kernel for e8m0 resmooth to reduce memory footprint #10327
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…print Signed-off-by: Nekofish-L <[email protected]>
📝 WalkthroughWalkthroughThe file replaces Python-based FP8 resmoothing logic with a Triton kernel implementation. The public Changes
Estimated code review effort🎯 3 (Moderate) | ⏱️ ~20 minutes Pre-merge checks and finishing touches❌ Failed checks (2 warnings)
✅ Passed checks (1 passed)
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tensorrt_llm/quantization/utils/fp8_utils.py (1)
1-1: Add the required NVIDIA copyright header.This file is missing the NVIDIA copyright header required by coding guidelines. The header should include the year 2025 (or appropriate year range) for this modification.
As per coding guidelines, all TensorRT-LLM code should contain an NVIDIA copyright header.
🔎 Suggested copyright header
Add at the beginning of the file:
+# SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + from typing import Optional, Tuple
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tensorrt_llm/quantization/utils/fp8_utils.py
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tensorrt_llm/quantization/utils/fp8_utils.py
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🧠 Learnings (2)
📓 Common learnings
Learnt from: jhaotingc
Repo: NVIDIA/TensorRT-LLM PR: 7856
File: cpp/tensorrt_llm/thop/fp8BlockScaleMoe.cpp:159-166
Timestamp: 2025-09-19T21:28:13.751Z
Learning: In TensorRT-LLM blockScaleMoe routing (cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/runner.cu), the DeepSeek routing method performs reinterpret_cast<float*>(routingLogits) at line 89, which could cause issues if routing_logits are BF16. However, Qwen3-FP8 models use RenormalizeNaive routing method and are not affected by this dtype casting issue.
Learnt from: venkywonka
Repo: NVIDIA/TensorRT-LLM PR: 6029
File: .github/pull_request_template.md:45-53
Timestamp: 2025-08-27T17:50:13.264Z
Learning: For PR templates in TensorRT-LLM, avoid suggesting changes that would increase developer overhead, such as converting plain bullets to mandatory checkboxes. The team prefers guidance-style bullets that don't require explicit interaction to reduce friction in the PR creation process.
Learnt from: djns99
Repo: NVIDIA/TensorRT-LLM PR: 6915
File: cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_kernels.cu:4010-4012
Timestamp: 2025-08-14T23:23:27.449Z
Learning: For MOE (Mixture of Experts) code reviews in TensorRT-LLM, avoid repeatedly suggesting finalize fusion validation checks and safety assertions. The user djns99 has indicated these suggestions are repetitive and unwanted across multiple MOE-related changes.
📚 Learning: 2025-09-19T21:28:13.751Z
Learnt from: jhaotingc
Repo: NVIDIA/TensorRT-LLM PR: 7856
File: cpp/tensorrt_llm/thop/fp8BlockScaleMoe.cpp:159-166
Timestamp: 2025-09-19T21:28:13.751Z
Learning: In TensorRT-LLM blockScaleMoe routing (cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/runner.cu), the DeepSeek routing method performs reinterpret_cast<float*>(routingLogits) at line 89, which could cause issues if routing_logits are BF16. However, Qwen3-FP8 models use RenormalizeNaive routing method and are not affected by this dtype casting issue.
Applied to files:
tensorrt_llm/quantization/utils/fp8_utils.py
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- GitHub Check: Pre-commit Check
| @triton.jit | ||
| def _resmooth_kernel( | ||
| w_ptr, | ||
| s_ptr, | ||
| M, | ||
| K, | ||
| stride_wm, | ||
| stride_wk, | ||
| stride_sm, | ||
| stride_sk, | ||
| BLOCK_M: tl.constexpr, | ||
| BLOCK_K: tl.constexpr, | ||
| ): | ||
| pid = tl.program_id(0) | ||
| num_pid_k = tl.cdiv(K, BLOCK_K) | ||
| pid_m = pid // num_pid_k | ||
| pid_k = pid % num_pid_k | ||
|
|
||
| s_offset = pid_m * stride_sm + pid_k * stride_sk | ||
| old_scale = tl.load(s_ptr + s_offset) | ||
|
|
||
| rm = pid_m * BLOCK_M + tl.arange(0, BLOCK_M) | ||
| rk = pid_k * BLOCK_K + tl.arange(0, BLOCK_K) | ||
|
|
||
| w_mask = (rm[:, None] < M) & (rk[None, :] < K) | ||
| w_offsets = rm[:, None] * stride_wm + rk[None, :] * stride_wk | ||
| w_fp8 = tl.load(w_ptr + w_offsets, mask=w_mask, other=0.0) | ||
| w_fp32 = w_fp8.to(tl.float32) | ||
|
|
||
| w_val = w_fp32 * old_scale | ||
| block_amax = tl.maximum(tl.max(tl.abs(w_val)), 1e-4) | ||
|
|
||
| # E8M0 sf = 2 ^ ceil(log2(sf)) | ||
| new_scale = tl.math.exp2(tl.math.ceil(tl.math.log2(block_amax / 448.0))) | ||
| w_requant = w_val * (1.0 / new_scale) | ||
|
|
||
| tl.store(w_ptr + w_offsets, w_requant, mask=w_mask) | ||
| tl.store(s_ptr + s_offset, new_scale) | ||
|
|
There was a problem hiding this comment.
Critical: Batch dimension handling is broken in the kernel.
The kernel receives batched 3D tensors (w_view and s_view with shape (num_batches, M, K)) but only receives stride(1) and stride(2). The grid on Line 111-112 multiplies by num_batches, but the kernel doesn't extract the batch ID from pid or use batch strides. This causes incorrect indexing for multi-batch inputs.
🔎 Proposed fix
Add batch handling to the kernel:
@triton.jit
def _resmooth_kernel(
w_ptr,
s_ptr,
M,
K,
+ stride_wb,
stride_wm,
stride_wk,
+ stride_sb,
stride_sm,
stride_sk,
BLOCK_M: tl.constexpr,
BLOCK_K: tl.constexpr,
):
pid = tl.program_id(0)
+ num_pid_m = tl.cdiv(M, BLOCK_M)
num_pid_k = tl.cdiv(K, BLOCK_K)
- pid_m = pid // num_pid_k
- pid_k = pid % num_pid_k
+ num_pid_per_batch = num_pid_m * num_pid_k
+
+ pid_batch = pid // num_pid_per_batch
+ pid_remainder = pid % num_pid_per_batch
+ pid_m = pid_remainder // num_pid_k
+ pid_k = pid_remainder % num_pid_k
- s_offset = pid_m * stride_sm + pid_k * stride_sk
+ s_offset = pid_batch * stride_sb + pid_m * stride_sm + pid_k * stride_sk
old_scale = tl.load(s_ptr + s_offset)
rm = pid_m * BLOCK_M + tl.arange(0, BLOCK_M)
rk = pid_k * BLOCK_K + tl.arange(0, BLOCK_K)
w_mask = (rm[:, None] < M) & (rk[None, :] < K)
- w_offsets = rm[:, None] * stride_wm + rk[None, :] * stride_wk
+ w_offsets = pid_batch * stride_wb + rm[:, None] * stride_wm + rk[None, :] * stride_wk
w_fp8 = tl.load(w_ptr + w_offsets, mask=w_mask, other=0.0)Update the kernel call on Line 114-125:
_resmooth_kernel[grid](
w_view,
s_view,
M,
K,
+ w_view.stride(0),
w_view.stride(1),
w_view.stride(2),
+ s_view.stride(0),
s_view.stride(1),
s_view.stride(2),
BLOCK_M=BLOCK_M,
BLOCK_K=BLOCK_K,
)📝 Committable suggestion
‼️ IMPORTANT
Carefully review the code before committing. Ensure that it accurately replaces the highlighted code, contains no missing lines, and has no issues with indentation. Thoroughly test & benchmark the code to ensure it meets the requirements.
| @triton.jit | |
| def _resmooth_kernel( | |
| w_ptr, | |
| s_ptr, | |
| M, | |
| K, | |
| stride_wm, | |
| stride_wk, | |
| stride_sm, | |
| stride_sk, | |
| BLOCK_M: tl.constexpr, | |
| BLOCK_K: tl.constexpr, | |
| ): | |
| pid = tl.program_id(0) | |
| num_pid_k = tl.cdiv(K, BLOCK_K) | |
| pid_m = pid // num_pid_k | |
| pid_k = pid % num_pid_k | |
| s_offset = pid_m * stride_sm + pid_k * stride_sk | |
| old_scale = tl.load(s_ptr + s_offset) | |
| rm = pid_m * BLOCK_M + tl.arange(0, BLOCK_M) | |
| rk = pid_k * BLOCK_K + tl.arange(0, BLOCK_K) | |
| w_mask = (rm[:, None] < M) & (rk[None, :] < K) | |
| w_offsets = rm[:, None] * stride_wm + rk[None, :] * stride_wk | |
| w_fp8 = tl.load(w_ptr + w_offsets, mask=w_mask, other=0.0) | |
| w_fp32 = w_fp8.to(tl.float32) | |
| w_val = w_fp32 * old_scale | |
| block_amax = tl.maximum(tl.max(tl.abs(w_val)), 1e-4) | |
| # E8M0 sf = 2 ^ ceil(log2(sf)) | |
| new_scale = tl.math.exp2(tl.math.ceil(tl.math.log2(block_amax / 448.0))) | |
| w_requant = w_val * (1.0 / new_scale) | |
| tl.store(w_ptr + w_offsets, w_requant, mask=w_mask) | |
| tl.store(s_ptr + s_offset, new_scale) | |
| @triton.jit | |
| def _resmooth_kernel( | |
| w_ptr, | |
| s_ptr, | |
| M, | |
| K, | |
| stride_wb, | |
| stride_wm, | |
| stride_wk, | |
| stride_sb, | |
| stride_sm, | |
| stride_sk, | |
| BLOCK_M: tl.constexpr, | |
| BLOCK_K: tl.constexpr, | |
| ): | |
| pid = tl.program_id(0) | |
| num_pid_m = tl.cdiv(M, BLOCK_M) | |
| num_pid_k = tl.cdiv(K, BLOCK_K) | |
| num_pid_per_batch = num_pid_m * num_pid_k | |
| pid_batch = pid // num_pid_per_batch | |
| pid_remainder = pid % num_pid_per_batch | |
| pid_m = pid_remainder // num_pid_k | |
| pid_k = pid_remainder % num_pid_k | |
| s_offset = pid_batch * stride_sb + pid_m * stride_sm + pid_k * stride_sk | |
| old_scale = tl.load(s_ptr + s_offset) | |
| rm = pid_m * BLOCK_M + tl.arange(0, BLOCK_M) | |
| rk = pid_k * BLOCK_K + tl.arange(0, BLOCK_K) | |
| w_mask = (rm[:, None] < M) & (rk[None, :] < K) | |
| w_offsets = pid_batch * stride_wb + rm[:, None] * stride_wm + rk[None, :] * stride_wk | |
| w_fp8 = tl.load(w_ptr + w_offsets, mask=w_mask, other=0.0) | |
| w_fp32 = w_fp8.to(tl.float32) | |
| w_val = w_fp32 * old_scale | |
| block_amax = tl.maximum(tl.max(tl.abs(w_val)), 1e-4) | |
| # E8M0 sf = 2 ^ ceil(log2(sf)) | |
| new_scale = tl.math.exp2(tl.math.ceil(tl.math.log2(block_amax / 448.0))) | |
| w_requant = w_val * (1.0 / new_scale) | |
| tl.store(w_ptr + w_offsets, w_requant, mask=w_mask) | |
| tl.store(s_ptr + s_offset, new_scale) |
🤖 Prompt for AI Agents
In tensorrt_llm/quantization/utils/fp8_utils.py around lines 54 to 92, the
kernel ignores the batch dimension so multi-batch inputs index incorrectly;
update the kernel to extract a batch id from tl.program_id(0) and compute
pid_m/pid_k relative to the per‑batch grid, add batch strides (e.g. stride_wb
and stride_sb) as additional kernel arguments, and incorporate them into
s_offset and w_offsets (compute a batch_base for w_ptr and s_ptr using
batch*stride_wb / batch*stride_sb before adding pid_m/pid_k offsets). Also
update the kernel launch to pass num_batches and the new batch strides so each
program id indexes the correct (batch, m, k) block.
| def resmooth_to_fp8_e8m0( | ||
| weight: torch.Tensor, | ||
| weight_scale: torch.Tensor, | ||
| block_size: tuple[int, int] = (128, 128), | ||
| ): | ||
| assert weight.dtype == torch.float8_e4m3fn | ||
| assert weight_scale.dtype == torch.float32 | ||
|
|
||
| orig_shape = weight.shape | ||
| M, K = orig_shape[-2:] | ||
| w_view = weight.view(-1, M, K) | ||
| s_view = weight_scale.view(-1, weight_scale.shape[-2], | ||
| weight_scale.shape[-1]) | ||
|
|
||
| num_batches = w_view.shape[0] | ||
| BLOCK_M, BLOCK_K = block_size | ||
|
|
||
| grid = (num_batches * (triton.cdiv(M, BLOCK_M)) * | ||
| (triton.cdiv(K, BLOCK_K)), ) | ||
|
|
||
| _resmooth_kernel[grid]( | ||
| w_view, | ||
| s_view, | ||
| M, | ||
| K, | ||
| w_view.stride(1), | ||
| w_view.stride(2), | ||
| s_view.stride(1), | ||
| s_view.stride(2), | ||
| BLOCK_M=BLOCK_M, | ||
| BLOCK_K=BLOCK_K, | ||
| ) | ||
| # this is an in-place operation, however, we return for simplicity | ||
| return weight, weight_scale |
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🧩 Analysis chain
🏁 Script executed:
#!/bin/bash
# Find all calls to resmooth_to_fp8_e8m0
echo "=== Searching for resmooth_to_fp8_e8m0 calls ==="
rg -n 'resmooth_to_fp8_e8m0' --type=py -A 3 -B 1
echo ""
echo "=== Checking file header for copyright ==="
head -20 tensorrt_llm/quantization/utils/fp8_utils.pyRepository: NVIDIA/TensorRT-LLM
Length of output: 3302
Add NVIDIA copyright header to the file.
The file tensorrt_llm/quantization/utils/fp8_utils.py is missing the required NVIDIA copyright header. According to coding guidelines, all TensorRT-LLM code must contain an NVIDIA copyright header with the year of latest meaningful modification. Add the header at the top of the file before the imports.
Regarding the function signature change: All call sites in the codebase correctly use the new signature and are compatible with the default block_size=(128, 128) parameter. No signature updates are required at call sites.
🤖 Prompt for AI Agents
In tensorrt_llm/quantization/utils/fp8_utils.py around lines 94 to 127: add the
required NVIDIA copyright header at the very top of the file (before any
imports) with the correct year of latest meaningful modification and the
standard NVIDIA license phrasing used in this repo; ensure the header exactly
matches the project's header format and encoding, then save—no changes to the
function signature or any call sites are required since they are already
compatible with the default block_size.
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Background
The recent update to support per-block quantization on Blackwell architectures requires converting quantization scales to
FP8_E8M0format and adjusting weights accordingly. However, this conversion process was implemented in a memory-inefficient manner, creating a massive, temporary memory footprint.For example, when loading a model such as Qwen3-32B-FP8 with a TP2 configuration, the weight loading process alone consumed approximately 18 GB of GPU memory per gpu. However, the additional resmoothing step increased peak memory usage by an extra ~15 GB per GPU, making it impossible to load the model under the memory constraints of RTX5090.
Solution
This PR implements a fused triton kernel for e8m0 resmooth to reduce peak memory footprint.
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