[TRTLLM-10358][feat] Added proper rescaling of FP4 weights #10378
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Signed-off-by: greg-kwasniewski1 <[email protected]>
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📝 WalkthroughWalkthroughAdded an FP4 operation detection helper function and modified weight shape computation to account for FP4 storage format by multiplying the last dimension by 2 for FP4-quantized nodes. This ensures correct shape reporting for FP4-formatted weights during layer detection. Changes
Estimated code review effort🎯 2 (Simple) | ⏱️ ~10 minutes Pre-merge checks and finishing touches❌ Failed checks (2 warnings, 2 inconclusive)
✅ Passed checks (1 passed)
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tensorrt_llm/_torch/auto_deploy/utils/node_utils.py
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Files:
tensorrt_llm/_torch/auto_deploy/utils/node_utils.py
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Files:
tensorrt_llm/_torch/auto_deploy/utils/node_utils.py
🧠 Learnings (2)
📓 Common learnings
Learnt from: amitz-nv
Repo: NVIDIA/TensorRT-LLM PR: 8063
File: tensorrt_llm/lora_manager.py:1080-1112
Timestamp: 2025-09-29T15:14:28.503Z
Learning: In tensorrt_llm/lora_manager.py, when calculating part_sizes for attn_qkv fused LoRA modules, the sizes are correctly multiplied by tp_size because model_config.num_heads and model_config.num_kv_heads are already divided by tp_size (per-TP-rank values), so multiplication is needed to get the original full concatenated dimension size. The interleave_fused_lora_weights_for_tp function provides proper validation with asserts for total size and TP divisibility.
Learnt from: amitz-nv
Repo: NVIDIA/TensorRT-LLM PR: 8063
File: tensorrt_llm/lora_manager.py:1080-1112
Timestamp: 2025-09-29T15:14:28.503Z
Learning: In tensorrt_llm/lora_manager.py, when calculating part_sizes for attn_qkv fused LoRA modules, the sizes are correctly multiplied by tp_size because model_config.num_heads and model_config.num_kv_heads are already divided by tp_size (per-TP-rank values), so multiplication is needed to get the original full concatenated dimension size. The interleave_fused_lora_weights_for_tp function provides proper validation.
Learnt from: amitz-nv
Repo: NVIDIA/TensorRT-LLM PR: 8063
File: tensorrt_llm/lora_manager.py:1080-1112
Timestamp: 2025-09-29T15:14:28.503Z
Learning: In tensorrt_llm/lora_manager.py, when calculating part_sizes for attn_qkv fused LoRA modules, the sizes are correctly multiplied by tp_size because model_config.num_heads and model_config.num_kv_heads are already divided by tp_size (per-TP-rank values), so multiplication is needed to get the original full concatenated dimension size. The interleave_fused_lora_weights_for_tp function provides proper validation.
Learnt from: jhaotingc
Repo: NVIDIA/TensorRT-LLM PR: 7856
File: cpp/tensorrt_llm/thop/fp8BlockScaleMoe.cpp:159-166
Timestamp: 2025-09-19T21:28:13.751Z
Learning: In TensorRT-LLM blockScaleMoe routing (cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/runner.cu), the DeepSeek routing method performs reinterpret_cast<float*>(routingLogits) at line 89, which could cause issues if routing_logits are BF16. However, Qwen3-FP8 models use RenormalizeNaive routing method and are not affected by this dtype casting issue.
📚 Learning: 2025-11-14T11:22:03.729Z
Learnt from: nzmora-nvidia
Repo: NVIDIA/TensorRT-LLM PR: 9163
File: tensorrt_llm/_torch/auto_deploy/custom_ops/quant.py:107-113
Timestamp: 2025-11-14T11:22:03.729Z
Learning: In TensorRT-LLM AutoDeploy custom ops, when adding hardware capability checks to select between kernel implementations (e.g., cuBLAS vs. CUDA kernel), use descriptive variable names that identify the specific GPU architectures or families being targeted (e.g., `is_blackwell_geforce_or_ada`) rather than generic names like `enable_cuda_core`. This makes it clear that the code is selecting an implementation path based on hardware capabilities, not enabling/disabling hardware features.
Applied to files:
tensorrt_llm/_torch/auto_deploy/utils/node_utils.py
🧬 Code graph analysis (1)
tensorrt_llm/_torch/auto_deploy/utils/node_utils.py (1)
tensorrt_llm/_torch/auto_deploy/custom_ops/torch_quant.py (2)
torch_fake_quant_nvfp4_linear(208-266)torch_fake_quant_nvfp4_linear(270-279)
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- GitHub Check: Pre-commit Check
🔇 Additional comments (2)
tensorrt_llm/_torch/auto_deploy/utils/node_utils.py (2)
307-314: LGTM - FP4 operation detection helper.The function correctly identifies FP4 linear operations by checking for both the quantized and fake-quantized nvfp4 variants. This follows the established pattern of similar helper functions in the codebase.
746-759: Verify the fix resolves issue #10358.The FP4 weight rescaling ensures that layer detection logic compares logical shapes rather than packed storage shapes. This should prevent incorrect grouping of SSM blocks. Please verify that the fix resolves the AutoDeploy sharding failure on NemotronH hybrid models (e.g., NVIDIA-Nemotron-Nano-9B-v2-NVFP4) mentioned in issue #10358.
Run the reproduction command from the issue after applying this fix to confirm that:
- The assertion "SSM layer must have exactly one SSM node" no longer fails
- The model builds successfully under AutoDeploy
- Layer detection correctly identifies individual SSM blocks rather than grouping them
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Signed-off-by: greg-kwasniewski1 <[email protected]>
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Fixes #10358
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