[TRTLLM-8136][feat] Dynamic draft length in spec decode (stage 2).

[zheyuf]

@coderabbitai summary

Description

This PR updates the LLM API design from the dynamic draft length Stage 1 PR to improve CUDA graph compatibility. Aslo, this PR implements the CUDA graph capture logic and runtime Selection/Padding logic for dynamic draft length.

1. LLM API Design
   Users can specify a new field draft_len_schedule in spec_config.
   Example: {4:4, 8:2, 32:1, 64:0}.
   Logic:
   Batch Size 1-4 --> Draft Length 4
   Batch Size 5-8 --> Draft Length 2
   Batch Size 9-32 --> Draft Length 1
   Batch Size 33-64 --> Draft Length 0
   Constraint: All keys in draft_len_schedule must be present in cuda_graph_config.batch_sizes to align CUDA graph capturing behavior with the legacy (static) behavior.

2. CUDA Graph Capture
   We will only capture the specific (batch_size, draft_len) pairs defined by the schedule, rather than the full Cartesian product.
   Example: cuda_graph_config.batch_sizes = [1,2,3,4,5,6,7,8,16,24,32,64], max_draft_len = 4.
   New Behavior: with draft_len_schedule={4:4, 8:2, 32:1, 64:0}. Captures [(1,4),(2,4),(3,4),(4,4),(5,2),(6,2),(7,2),(8,2),(16,1),(24,1),(32,1),(64,0)].
   Legacy Behavior: Captures (BS, 4) for all batch sizes (plus extra graphs with draft len = 0 for disabled spec decode).
   This feature produces equal or lower graph capture overhead compared to the legacy behavior.

3. Runtime Selection/Padding Logic
   We use the pre-scheduling active batch size to determine the draft length.
   Example: If pre-scheduling BS = 10 --> Runtime DL = 1. We pad to the nearest round-up graph: (16, 1).
   Edge Case (Batch Size Decrease): Active batch size may drop after scheduling. We treat the determined runtime draft length as the source of truth and pad the batch size up to the nearest existing graph for that draft length.
   Scenario: Pre-schedule BS = 6 --> DL = 2. Post-schedule BS drops to 4.
   Resolution: We stick to DL = 2. Since (4, 2) was not captured (BS 4 maps to DL 4 in the schedule), we pad up to the nearest graph with DL 2, which is (5, 2).

Planned Timeline
Stage 1 (merged): LLM API design and drafter changes (ngram/model drafter). [PR] (Note: API in this stage1 PR is stale; updated in Stage 2).
Stage 2 (current): Target side changes (CUDA graph capture and selection/padding logic). Also update the llm api design.
Stage 3 (future): Perf study and extend to Chain Drafter.

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[zheyuf]

/bot run --disable-fail-fast

[tensorrt-cicd]

PR_Github #25787 [ run ] triggered by Bot. Commit: 5a7a837

[tensorrt-cicd]

PR_Github #25787 [ run ] completed with state SUCCESS. Commit: 5a7a837
/LLM/main/L0_MergeRequest_PR pipeline #19561 completed with status: 'FAILURE'

[zheyuf]

/bot run --disable-fail-fast

[zheyuf]

/bot run --disable-fail-fast

[tensorrt-cicd]

PR_Github #25875 [ run ] triggered by Bot. Commit: feff6ee

[tensorrt-cicd]

PR_Github #25875 [ run ] completed with state SUCCESS. Commit: feff6ee
/LLM/main/L0_MergeRequest_PR pipeline #19621 completed with status: 'FAILURE'

[zheyuf]

Close the PR as we shift focus to one model path.