[https://nvbugs/5644632][fix] Use correct memory pool#9196
[https://nvbugs/5644632][fix] Use correct memory pool#9196HuiGao-NV wants to merge 4 commits intoNVIDIA:mainfrom
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📝 WalkthroughWalkthroughThis PR refactors CUDA memory pool handling across the TensorRT-LLM PyTorch integration by introducing explicit Changes
Estimated code review effort🎯 3 (Moderate) | ⏱️ ~20–25 minutes
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✅ Passed checks (1 passed)
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Actionable comments posted: 1
🧹 Nitpick comments (1)
tensorrt_llm/_torch/memory_buffer_utils.py (1)
60-81: Consider adding a comment to clarify the reserved block preference logic.The conditional at lines 72-73 correctly ensures that a reserved block is not superseded by an unreserved one during best-fit search. However, the nested logic could be clearer for future maintainers.
Consider adding a comment:
# Find the smallest buffer that is still large enough (best-fit). if block.buffer.numel() < smallest_sufficient_size: + # Prefer reserved blocks: don't replace a reserved best-fit with an unreserved candidate if best_fit_block is not None and best_fit_block.is_reserved and not block.is_reserved: continue
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📒 Files selected for processing (5)
tensorrt_llm/_torch/compilation/backend.py(2 hunks)tensorrt_llm/_torch/memory_buffer_utils.py(1 hunks)tensorrt_llm/_torch/pyexecutor/cuda_graph_runner.py(4 hunks)tensorrt_llm/_torch/pyexecutor/model_engine.py(1 hunks)tests/integration/test_lists/waives.txt(0 hunks)
💤 Files with no reviewable changes (1)
- tests/integration/test_lists/waives.txt
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🧠 Learnings (4)
📓 Common learnings
Learnt from: nv-lschneider
Repo: NVIDIA/TensorRT-LLM PR: 7910
File: cpp/tensorrt_llm/kernels/nccl_device/multimem.h:20-30
Timestamp: 2025-09-23T15:13:48.819Z
Learning: TRT-LLM targets modern CUDA toolkits that support FP8 datatypes, so cuda_fp8.h can be included unconditionally without version guards in TRT-LLM code.
📚 Learning: 2025-08-26T09:37:10.463Z
Learnt from: jiaganc
Repo: NVIDIA/TensorRT-LLM PR: 7031
File: tensorrt_llm/bench/dataclasses/configuration.py:90-104
Timestamp: 2025-08-26T09:37:10.463Z
Learning: In TensorRT-LLM's bench configuration, the `get_pytorch_perf_config()` method returns `self.pytorch_config` which is a Dict[str, Any] that can contain default values including `cuda_graph_config`, making the fallback `llm_args["cuda_graph_config"]` safe to use.
Applied to files:
tensorrt_llm/_torch/pyexecutor/cuda_graph_runner.pytensorrt_llm/_torch/pyexecutor/model_engine.py
📚 Learning: 2025-08-19T12:45:11.997Z
Learnt from: amitz-nv
Repo: NVIDIA/TensorRT-LLM PR: 7033
File: tensorrt_llm/_torch/pyexecutor/model_engine.py:0-0
Timestamp: 2025-08-19T12:45:11.997Z
Learning: In tensorrt_llm/_torch/pyexecutor/model_engine.py, DoRA (Delta Orthogonal Rank Adaptation) functionality was removed from the PyTorch flow to eliminate issues with inverted DoRA detection logic. The original is_dora condition was checking if scaling_vec_pointer == 0, which was potentially incorrect.
Applied to files:
tensorrt_llm/_torch/pyexecutor/model_engine.py
📚 Learning: 2025-08-26T09:37:10.463Z
Learnt from: jiaganc
Repo: NVIDIA/TensorRT-LLM PR: 7031
File: tensorrt_llm/bench/dataclasses/configuration.py:90-104
Timestamp: 2025-08-26T09:37:10.463Z
Learning: In TensorRT-LLM, the `get_pytorch_perf_config()` method returns `self.pytorch_config` which can contain default `cuda_graph_config` values, so `llm_args` may already have this config before the extra options processing.
Applied to files:
tensorrt_llm/_torch/pyexecutor/model_engine.py
🧬 Code graph analysis (1)
tensorrt_llm/_torch/memory_buffer_utils.py (1)
tensorrt_llm/_utils.py (1)
numel(1009-1010)
⏰ Context from checks skipped due to timeout of 90000ms. You can increase the timeout in your CodeRabbit configuration to a maximum of 15 minutes (900000ms). (1)
- GitHub Check: Pre-commit Check
🔇 Additional comments (6)
tensorrt_llm/_torch/pyexecutor/cuda_graph_runner.py (4)
64-64: LGTM: Type annotation improved.Changing the type from
Anytotorch.cuda.MemPoolmakes the expected type explicit and improves type safety.
298-298: LGTM: Correct use of memory pool handle.The graph capture correctly uses
memory_pool_handlefor the pool parameter, aligning with the new handle-based approach.
431-432: LGTM: Proper cleanup of memory pool handle.The cleanup correctly deletes and nullifies the
memory_pool_handle, ensuring resources are properly released.
101-103: Fix syntax error: stray closing parenthesis.Line 102 contains a stray closing parenthesis that will cause a syntax error. Line 101 is a complete statement and doesn't require this.
Apply this diff:
self.memory_pool = config.cuda_graph_mem_pool if config.cuda_graph_mem_pool else torch.cuda.MemPool() -) self.memory_pool_handle = self.memory_pool.idLikely an incorrect or invalid review comment.
tensorrt_llm/_torch/compilation/backend.py (2)
26-27: LGTM: Explicit MemPool lifecycle management.Adding
_graph_poolas a class attribute enables explicit management of the CUDA memory pool lifecycle, which is cleaner than relying on implicit pool handles alone.
62-63: LGTM: Correct MemPool initialization.The initialization correctly creates a
MemPoolinstance and stores itsidas the handle, replacing the previous directgraph_pool_handle()call with explicit pool management.
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Signed-off-by: Hui Gao <huig@nvidia.com>
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Signed-off-by: Hui Gao <huig@nvidia.com>
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| best_fit_block.is_reserved = True | ||
| # A suitable buffer was found, so reuse it. | ||
| return self._view_as(best_fit_block.buffer, tensor_shape, dtype) | ||
| # else: |
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Just directly remove the commented out code?
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PR Follows TRT-LLM CODING GUIDELINES to the best of your knowledge.
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