Task: Figure out cache clock timing

[ShinyMiraidon]

Need to figure out how many separate clocks we need and what the timing for the clocks will be

[ShinyMiraidon]

Because the cache and register modules need to be clocked in between latch clocks, I am thinking that the cache clock is just an inverted version of the regular system clock so that the cache clocks on the negedge of the system clock. The same thing could be accomplished by changing the cache and register modules to use the negedge of the system clock but for now I want to keep the cache clock semi-independent in case it needs to be tuned later on.