docs(dn): James Jin S25 bulk upload part 1 (#364)

Author: jamesjin0516

src/design_notebooks/2025spring/gj2148.md

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+# Design notebook for James Jin (2025 Spring)
+## Feb. 10th - Mar. 16th, 2025
+### Work done
+(Awaiting assignment of tasks due to scheduling conflict and being unable to participate in weekly meetings) 
+### Working comments
+This semester due to TA responsabilities, I cannot attend the weekly meetings for the VIP and thus waited for separate communication from leadership about tasks for this semester. Now I have understood this semester's focus being building a Verilog implementation of a [simple processor known as RiSC](https://user.eng.umd.edu/~blj/risc/).
+
+## Mar. 17th - Mar. 23rd, 2025
+### Work done
+- [Reviewing RiSC specifications](https://user.eng.umd.edu/~blj/risc/RiSC-isa.pdf): understanding the instructions, registers, and memory of the processor.
+- Implementing RiSC's program counter and registers in Verilog: in progress
+### Working comments
+I have taken note of RiSC's register layout and began drafting up two Verilog modules. So far I am following along the [VIP's outlines](https://github.com/NYU-Processor-Design/nyu-processor-design.github.io/tree/185b4795936a7079428277a00e1476eda72ff4c2/src/getting_started/mini-proc) for these modules, which clarifies their inputs and outputs.
+
+## Mar. 24th - Mar. 30th, 2025
+### Work done
+- [RiSC Implementation](https://github.com/jamesjin0516/NYU_ProcDsgn_RiSC/tree/3010b13b8285b30be7d1cab05d943d0f257ce7fb): program counter and register files finished
+### Working comments
+I finished up the the implementation of the two RiSC modules started last week. Specifically with the reigster file, it's important to keep the value of register 0 as 0. It was a good refresher for Verilog syntax.
+
+## Mar. 31st - Apr. 6th, 2025
+### Work done
+- [RiSC Implementation](https://github.com/jamesjin0516/NYU_ProcDsgn_RiSC/tree/3168030c9be0bbdfbd8038ed2a9f8dfc965a10ab): data and instruction memory finished
+### Working comments
+Using the [VIP's directions](https://github.com/NYU-Processor-Design/nyu-processor-design.github.io/blob/185b4795936a7079428277a00e1476eda72ff4c2/src/getting_started/mini-proc/week2.md) on the capacity of data and instruction memory, I implemented the mechanisms for reading from memory and writing to it in the case of data memory.
+
+## Apr. 7th - Apr. 13th, 2025
+### Work done
+- [RiSC Implementation](https://github.com/jamesjin0516/NYU_ProcDsgn_RiSC/tree/b03e01fdb5a69faa28d2fa8dd748780a94bcb3f7): arithmetic logic unit finished
+### working comments
+This week I built the arithmetic logic unit (ALU) of RiSC. I had to refer to [documentation](https://user.eng.umd.edu/~blj/risc/RiSC-seq.pdf) of how different instructions should be executed, and once I knew the purpose of different flags and the roles of the ALU, the arithmetic was quick to implement.