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@@ -21,3 +21,7 @@ I thought I updated this but apparently it isn't here. Didn't get project work d
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## Week Seven:
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Did not get any project work done this week due to many homework assignments as I returned from break. Met during thursday meeting to update Rielle on our project. Going to try to get instruction memory done this week or next, but there's lots of work coming up for me outside of the VIP. I will do my best to get everything done.
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## Week Eight:
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Project Work: Wrote Instruction Memory. Used Srijan's version for help since I wasn't sure. I feel like I need better verilog fundamentals to understand fully what's going on. I don't feel like each of these components should take as long as they do, or be as unaproachable to me as they are. Not sure what I can do to improve that.
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Link for our RIsC-16 project repo: https://github.com/Noahms12/RiSC-16-project
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