[X86][NFC] X86CompressEVEX.cpp - Simplify code after 0c623b5

Author: KanRobert

llvm/lib/Target/X86/X86CompressEVEX.cpp

@@ -225,24 +225,25 @@ static bool CompressEVEXImpl(MachineInstr &MI, const X86Subtarget &ST) {
   //
   // For AVX512 cases, EVEX prefix is needed in order to carry this information
   // thus preventing the transformation to VEX encoding.
-  // MOVBE*rr is special because it has semantic of NDD but not set EVEX_B.
-  bool IsMovberr =
-      MI.getOpcode() == X86::MOVBE32rr || MI.getOpcode() == X86::MOVBE64rr;
+  unsigned Opc = MI.getOpcode();
   bool IsND = X86II::hasNewDataDest(TSFlags);
-  if ((TSFlags & X86II::EVEX_B) || IsMovberr)
-    if ((!IsND && !IsMovberr) || !isRedundantNewDataDest(MI, ST))
-      return false;
+  if (TSFlags & X86II::EVEX_B && !IsND)
+    return false;
+  // MOVBE*rr is special because it has semantic of NDD but not set EVEX_B.
+  bool IsNDLike = IsND || Opc == X86::MOVBE32rr || Opc == X86::MOVBE64rr;
+  if (IsNDLike && !isRedundantNewDataDest(MI, ST))
+    return false;
 
   ArrayRef<X86CompressEVEXTableEntry> Table = ArrayRef(X86CompressEVEXTable);
 
-  unsigned Opc = MI.getOpcode();
+  Opc = MI.getOpcode();
   const auto *I = llvm::lower_bound(Table, Opc);
   if (I == Table.end() || I->OldOpc != Opc) {
-    assert(!IsND && "Missing entry for ND instruction");
+    assert(!IsNDLike && "Missing entry for ND-like instruction");
     return false;
   }
 
-  if (!IsND && !IsMovberr) {
+  if (!IsNDLike) {
     if (usesExtendedRegister(MI) || !checkPredicate(I->NewOpc, &ST) ||
         !performCustomAdjustments(MI, I->NewOpc))
       return false;
@@ -267,7 +268,7 @@ static bool CompressEVEXImpl(MachineInstr &MI, const X86Subtarget &ST) {
     llvm_unreachable("Unknown EVEX compression");
   }
   MI.setAsmPrinterFlag(AsmComment);
-  if (IsND || IsMovberr)
+  if (IsNDLike)
     MI.tieOperands(0, 1);
 
   return true;