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TEST3_nativelink_simulation.rpt
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22 lines (18 loc) · 1013 Bytes
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Info: Start Nativelink Simulation process
========= EDA Simulation Settings =====================
Sim Mode : Gate
Family : cyclonev
Quartus root : c:/intelfpga_lite/20.1/quartus/bin64/
Quartus sim root : c:/intelfpga_lite/20.1/quartus/eda/sim_lib
Simulation Tool : modelsim-altera
Simulation Language : systemverilog
Simulation Mode : GUI
Sim Output File : TEST3.svo
Sim SDF file : TEST3__verilog.sdo
Sim dir : simulation\modelsim
=======================================================
Info: Starting NativeLink simulation with ModelSim-Altera software
Sourced NativeLink script c:/intelfpga_lite/20.1/quartus/common/tcl/internal/nativelink/modelsim.tcl
Warning: File TEST3_run_msim_gate_systemverilog.do already exists - backing up current file as TEST3_run_msim_gate_systemverilog.do.bak3
Info: Spawning ModelSim-Altera Simulation software
Info: NativeLink simulation flow was successful