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Merge remote-tracking branch 'origin/GP-5945_emteere_e500IncludedExtensionFixes--SQUASHED' into patch
2 parents daec88b + f391ddb commit 8689672

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‎Ghidra/Processors/PowerPC/data/languages/SPE_APU.sinc‎

Lines changed: 107 additions & 260 deletions
Large diffs are not rendered by default.

‎Ghidra/Processors/PowerPC/data/languages/SPE_EFV.sinc‎

Lines changed: 29 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1137,9 +1137,9 @@
11371137

11381138
# evlwhe RT,D(RA)
11391139
# evlwhe rT,rA,UI
1140-
:evlwhe D,EVUIMM_4_RAt is OP=4 & D & EVUIMM_4_RAt & RA_OR_ZERO & UI & XOP_0_10=785
1140+
:evlwhe D,EVUIMM_4_RAt is OP=4 & D & EVUIMM_4_RAt & XOP_0_10=785
11411141
{
1142-
ea:$(REGISTER_SIZE) = RA_OR_ZERO + (UI * 4);
1142+
ea:$(REGISTER_SIZE) = EVUIMM_4_RAt;
11431143

11441144
# move results into upper and lower words
11451145
tmpZ:8 = zext( *:2(ea + 2) );
@@ -1179,9 +1179,9 @@
11791179
# ISA-info: evlwwsplat - Form "EVX" Page 521 Category "SP"
11801180
# binutils: NO-EXAMPLE - evlwwsplat
11811181
# collides with maclhwu
1182-
:evlwwsplat D,EVUIMM_4_RAt is OP=4 & D & RA_OR_ZERO & EVUIMM_4_RAt & UI & XOP_0_10=793
1182+
:evlwwsplat D,EVUIMM_4_RAt is OP=4 & D & EVUIMM_4_RAt & XOP_0_10=793
11831183
{
1184-
ea:$(REGISTER_SIZE) = RA_OR_ZERO + (UI * 4);
1184+
ea:$(REGISTER_SIZE) = EVUIMM_4_RAt;
11851185

11861186
# move results into upper and lower words
11871187
tmpZ:8 = zext( *:4(ea) );
@@ -1413,10 +1413,34 @@
14131413
tmpAL:8 = zext( A:4 );
14141414
tmpBL:8 = zext( B:4 );
14151415

1416-
D = tmpAL * tmpBL;
1416+
temp:8 = tmpAL * tmpBL;
1417+
D = temp;
14171418
}
14181419

1420+
# evmwumia RT,RA,RB
1421+
# ISA-cmt: Vector Multiply Word Unsigned, Modulo, Integer to Accumulator
1422+
# evmwumia rD,rA,rB 100 01A1 1000 A=1
1423+
:evmwumia D,A,B is OP=4 & A & B & D & XOP_0_10=0x478 {
1424+
tmpAL:8 = zext( A:4 );
1425+
tmpBL:8 = zext( B:4 );
1426+
1427+
temp:8 = tmpAL * tmpBL;
1428+
D = temp;
1429+
ACC = D;
1430+
}
14191431

1432+
# evmwumiaa RT,RA,RB
1433+
# ISA-cmt: Vector Multiply Word Unsigned, Modulo, Integer and Accumulate
1434+
# evmwumiaa rD,rA,rB 101 0101 1000
1435+
# evmwumiaa confict with macchwo
1436+
:evmwumiaa D,A,B is OP=4 & A & B & D & XOP_0_10=0x558 {
1437+
tmpAL:8 = zext( A:4 );
1438+
tmpBL:8 = zext( B:4 );
1439+
1440+
temp:8 = tmpAL * tmpBL;
1441+
D = ACC + temp;
1442+
ACC = D;
1443+
}
14201444

14211445
# =================================================================
14221446
# Page 547

‎Ghidra/Processors/PowerPC/data/languages/evx.sinc‎

Lines changed: 0 additions & 114 deletions
Original file line numberDiff line numberDiff line change
@@ -4,120 +4,6 @@
44
@include "SPE_APU.sinc"
55
@endif
66

7-
define pcodeop vectorExclusiveOr;
8-
define pcodeop vectorMergeHigh;
9-
define pcodeop vectorMergeLow;
10-
define pcodeop vectorLoadDoubleWordIntoDoubleWordIndexed;
11-
define pcodeop vectorStoreDoubleOfDoubleIndexed;
12-
define pcodeop initializeAccumulator;
13-
define pcodeop vectorShiftRightWordSigned;
14-
define pcodeop vectorShiftRightWordUnsigned;
15-
16-
:evxor vrD_64_0,vrA_64_0,vrB_64_0 is OP=4 & vrD_64_0 & vrA_64_0 & vrB_64_0 & XOP_0_10=534
17-
{
18-
vrD_64_0 = vrA_64_0 ^ vrB_64_0;
19-
}
20-
21-
@if REGISTER_SIZE=="8"
22-
:evmergehi S,A,B is OP=4 & S & A & B & XOP_0_10=556
23-
{
24-
S[32,32] = A[32,32];
25-
S[ 0,32] = B[ 0,32];
26-
}
27-
28-
:evmergelo S,A,B is OP=4 & S & A & B & XOP_0_10=557
29-
{
30-
S[32,32] = A[0,32];
31-
S[ 0,32] = B[0,32];
32-
}
33-
@endif
34-
35-
36-
:evldd RT,dUI16PlusRAOrZeroAddress is OP=4 & RT & dUI16PlusRAOrZeroAddress & XOP_0_10=769
37-
{
38-
ea:$(REGISTER_SIZE) = dUI16PlusRAOrZeroAddress;
39-
RT = *:8 ($(EATRUNC));
40-
}
41-
42-
:evlddx RT,RA_OR_ZERO,RB is OP=4 & RT & RA_OR_ZERO & RB & XOP_0_10=768
43-
{
44-
ea:$(REGISTER_SIZE) = RA_OR_ZERO + RB;
45-
RT = *:8 ($(EATRUNC));
46-
}
47-
48-
@if REGISTER_SIZE=="8"
49-
@ifndef IS_ISA
50-
:evsrws S,A,B is OP=4 & S & A & B & XOP_0_10=545
51-
{
52-
local low:4 = A[0,32];
53-
local high:4 = A[32,32];
54-
local low_shift:1 = B[0,5];
55-
local high_shift:1 = B[32,5];
56-
S[0,32] = low s>> zext(low_shift);
57-
S[32,32] = high s>> zext(high_shift);
58-
}
59-
@endif
60-
61-
@ifndef IS_ISA
62-
:evsrwu S,A,B is OP=4 & S & A & B & XOP_0_10=544
63-
{
64-
local low:4 = A[0,32];
65-
local high:4 = A[32,32];
66-
local low_shift:1 = B[0,5];
67-
local high_shift:1 = B[32,5];
68-
S[0,32] = low >> zext(low_shift);
69-
S[32,32] = high >> zext(high_shift);
70-
}
71-
@endif
72-
@endif
73-
74-
:evstdd RS,dUI16PlusRAOrZeroAddress is OP=4 & RS & dUI16PlusRAOrZeroAddress & XOP_0_10=801
75-
{
76-
ea:$(REGISTER_SIZE) = dUI16PlusRAOrZeroAddress;
77-
*:8 ($(EATRUNC)) = RS;
78-
}
79-
80-
:evstddx RS,RA_OR_ZERO,RB is OP=4 & RS & RA_OR_ZERO & RB & XOP_0_10=800
81-
{
82-
ea:$(REGISTER_SIZE) = RA_OR_ZERO + RB;
83-
*:8 ($(EATRUNC)) = RS;
84-
}
85-
86-
:evmra RT,RA is OP=4 & RT & RA & BITS_11_15=0 & XOP_0_10=1220
87-
{
88-
ACC = zext(RA);
89-
RT = RA;
90-
}
91-
92-
@if REGISTER_SIZE=="8"
93-
# evmergehilo rD,rA,rB 010 0010 1110
94-
:evmergehilo S,A,B is OP=4 & S & A & B & XOP_0_10=558 {
95-
S[32,32] = A[32,32];
96-
S[ 0,32] = B[ 0,32];
97-
98-
}
99-
100-
# evmergelohi rD,rA,rB 010 0010 1111
101-
:evmergelohi S,A,B is OP=4 & S & A & B & XOP_0_10=559 {
102-
S[32,32] = A[ 0,32];
103-
S[ 0,32] = B[32,32];
104-
}
105-
@endif
106-
107-
# evstwwe rS,rA,UIMM 011 0011 1001
108-
:evstwwe RS,dUI16PlusRAOrZeroAddress is OP=4 & RS & dUI16PlusRAOrZeroAddress & XOP_0_10=0x339
109-
{
110-
ea:$(REGISTER_SIZE) = dUI16PlusRAOrZeroAddress;
111-
*:4 ($(EATRUNC)) = RS:4;
112-
}
113-
114-
# evstwwex rS,rA,rB 011 0011 1000
115-
:evstwwex RS,RA_OR_ZERO,RB is OP=4 & RS & RA_OR_ZERO & RB & XOP_0_10=0x338
116-
{
117-
ea:$(REGISTER_SIZE) = RA_OR_ZERO + RB;
118-
*:4 ($(EATRUNC)) = RS:4;
119-
}
120-
1217
:lvx vrD, RA_OR_ZERO, RB is OP=31 & vrD & RA_OR_ZERO & RB & XOP_1_10=103 & BIT_0=0
1228
{
1239
ea:$(REGISTER_SIZE) = RA_OR_ZERO + RB;

‎Ghidra/Processors/PowerPC/data/languages/ppc_32_e500_be.slaspec‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
# by the actual processor (e.g., floating pointer registers and associated instructions).
55
# The actual processor only supports a subset of the registers and instructions implemented.
66

7-
@define E500
7+
@define E500 "1"
88

99
@define ENDIAN "big"
1010

@@ -19,10 +19,11 @@
1919

2020
@define CTR_OFFSET "32"
2121

22-
@define NoLegacyIntegerMultiplyAccumulate
22+
@define NoLegacyIntegerMultiplyAccumulate "1"
2323

2424
@include "ppc_common.sinc"
2525
@include "quicciii.sinc"
26+
@include "SPE_APU.sinc"
2627
@include "evx.sinc"
2728
@include "SPEF_SCR.sinc"
2829
@include "SPE_EFSD.sinc"

‎Ghidra/Processors/PowerPC/data/languages/ppc_32_e500_le.slaspec‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
# by the actual processor (e.g., floating pointer registers and associated instructions).
55
# The actual processor only supports a subset of the registers and instructions implemented.
66

7-
@define E500
7+
@define E500 "1"
88

99
@define ENDIAN "little"
1010

@@ -19,10 +19,11 @@
1919

2020
@define CTR_OFFSET "32"
2121

22-
@define NoLegacyIntegerMultiplyAccumulate
22+
@define NoLegacyIntegerMultiplyAccumulate "1"
2323

2424
@include "ppc_common.sinc"
2525
@include "quicciii.sinc"
26+
@include "SPE_APU.sinc"
2627
@include "evx.sinc"
2728
@include "SPEF_SCR.sinc"
2829
@include "SPE_EFSD.sinc"

‎Ghidra/Processors/PowerPC/data/languages/ppc_32_e500mc_be.slaspec‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,7 @@
1414
#
1515
@define CTR_OFFSET "32"
1616

17-
@define NoLegacyIntegerMultiplyAccumulate
17+
@define NoLegacyIntegerMultiplyAccumulate "1"
1818

1919
@include "ppc_common.sinc"
2020
@include "quicciii.sinc"

‎Ghidra/Processors/PowerPC/data/languages/ppc_32_e500mc_le.slaspec‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@
1212
#
1313
@define CTR_OFFSET "32"
1414

15-
@define NoLegacyIntegerMultiplyAccumulate
15+
@define NoLegacyIntegerMultiplyAccumulate "1"
1616

1717
@include "ppc_common.sinc"
1818
@include "quicciii.sinc"

‎Ghidra/Processors/PowerPC/data/languages/ppc_common.sinc‎

Lines changed: 8 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1064,9 +1064,14 @@ define token instrvle(16)
10641064
LK0_VLE=(0,0)
10651065
;
10661066

1067-
EVUIMM_2_RAt: val^"("^A^")" is A & EVUIMM_2 [ val = EVUIMM_2*2; ] { tmp:4 = A+(EVUIMM_2*2); export tmp; }
1068-
EVUIMM_4_RAt: val^"("^A^")" is A & EVUIMM_4 [ val = EVUIMM_4*4; ] { tmp:4 = A+(EVUIMM_4*4); export tmp; }
1069-
EVUIMM_8_RAt: val^"("^A^")" is A & EVUIMM_8 [ val = EVUIMM_8*8; ] { tmp:4 = A+(EVUIMM_8*8); export tmp; }
1067+
EVUIMM_2_RAt: val^"("^RA^")" is RA & A & EVUIMM_2 [ val = EVUIMM_2*2; ] { tmp:$(REGISTER_SIZE) = RA+zext(val:4); export tmp; }
1068+
EVUIMM_2_RAt: val^"("^RA^")" is RA & A=0 & EVUIMM_2 [ val = EVUIMM_2*2; ] { tmp:$(REGISTER_SIZE) = zext(val:4); export tmp; }
1069+
1070+
EVUIMM_4_RAt: val^"("^RA^")" is RA & A & EVUIMM_4 [ val = EVUIMM_4*4; ] { tmp:$(REGISTER_SIZE) = RA+zext(val:4); export tmp; }
1071+
EVUIMM_4_RAt: val^"("^RA^")" is RA & A=0 & EVUIMM_4 [ val = EVUIMM_4*4; ] { tmp:$(REGISTER_SIZE) = zext(val:4); export tmp; }
1072+
1073+
EVUIMM_8_RAt: val^"("^RA^")" is RA & A & EVUIMM_8 [ val = EVUIMM_8*8; ] { tmp:$(REGISTER_SIZE) = RA+zext(val:4); export tmp; }
1074+
EVUIMM_8_RAt: val^"("^RA^")" is RA & A=0 & EVUIMM_8 [ val = EVUIMM_8*8; ] { tmp:$(REGISTER_SIZE) = zext(val:4); export tmp; }
10701075

10711076
attach variables [ T ]
10721077
[ vs0 vs1 vs2 vs3 vs4 vs5 vs6 vs7 vs8 vs9 vs10 vs11 vs12 vs13 vs14 vs15

‎Ghidra/Processors/PowerPC/data/languages/ppc_embedded.sinc‎

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -49,6 +49,13 @@
4949
dataCacheBlockClearToZero(ea);
5050
}
5151

52+
#dcbzl 0,r0 0x7c 20 07 ec
53+
:dcbzl RA_OR_ZERO,B is OP=31 & BITS_21_25=1 & B & XOP_1_10=1014 & BIT_0=0 & RA_OR_ZERO
54+
{
55+
ea:$(REGISTER_SIZE) = RA_OR_ZERO + B;
56+
dataCacheBlockClearToZero(ea);
57+
}
58+
5259
define pcodeop memoryBarrier;
5360
#mbar 0 7c 00 06 ac
5461
:mbar MO is OP=31 & MO & XOP_1_10=854

‎Ghidra/Processors/PowerPC/data/languages/ppc_vle.sinc‎

Lines changed: 13 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -829,35 +829,35 @@ IMM16B: val is IMM_0_10_VLE & IMM_16_20_VLE [ val = (IMM_16_20_VLE << 11) |
829829
tmpS:4 = S:4;
830830
tmpA:4 = (tmpS << SHL) | (tmpS >> (32 - SHL));
831831

832-
tmpM1 = (~0:4) << MBL;
833-
tmpM1 = tmpM1 >> ((31-ME) + MBL);
834-
tmpM1 = tmpM1 << (31-ME);
832+
tmpM1:4 = (~0:4) << MBL;
833+
tmpM1 = tmpM1 >> ((31-ME) + MBL);
834+
tmpM1 = tmpM1 << (31-ME);
835835

836-
tmpM2 = (~0:4) << ME;
837-
tmpM2 = tmpM2 >> ((31-MBL) + ME);
838-
tmpM2 = tmpM2 << (31-MBL);
839-
tmpM2 = ~tmpM2;
836+
tmpM2:4 = (~0:4) << ME;
837+
tmpM2 = tmpM2 >> ((31-MBL) + ME);
838+
tmpM2 = tmpM2 << (31-MBL);
839+
tmpM2 = ~tmpM2;
840840

841841
local invert = (ME:1 < MBL:1);
842-
tmpM = (zext(invert == 0)*tmpM1) + (zext(invert == 1)*tmpM2);
842+
tmpM:4 = (zext(invert == 0)*tmpM1) + (zext(invert == 1)*tmpM2);
843843
A = zext(tmpA & tmpM) | (A & zext(~tmpM));
844844
}
845845

846846
:e_rlwinm A,S,SHL,MBL,ME is $(ISVLE) & OP=29 & BIT_0=1 & MBL & ME & A & SHL & S {
847847
tmpS:4 = S:4;
848848
tmpA:4 = (tmpS << SHL) | (tmpS >> (32 - SHL));
849849

850-
tmpM1 = (~0:4) << MBL;
851-
tmpM1 = tmpM1 >> ((31-ME) + MBL);
852-
tmpM1 = tmpM1 << (31-ME);
850+
tmpM1:4 = (~0:4) << MBL;
851+
tmpM1 = tmpM1 >> ((31-ME) + MBL);
852+
tmpM1 = tmpM1 << (31-ME);
853853

854-
tmpM2 = (~0:4) << ME;
854+
tmpM2:4 = (~0:4) << ME;
855855
tmpM2 = tmpM2 >> ((31-MBL) + ME);
856856
tmpM2 = tmpM2 << (31-MBL);
857857
tmpM2 = ~tmpM2;
858858

859859
local invert = (ME:1 < MBL:1);
860-
tmpM = (zext(invert == 0)*tmpM1) + (zext(invert == 1)*tmpM2);
860+
tmpM:4 = (zext(invert == 0)*tmpM1) + (zext(invert == 1)*tmpM2);
861861
A = zext(tmpA & tmpM);
862862
}
863863

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