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Add STM32F030 support. (#25)
* Add STM32F030 support. This means we can't use 32-bit TIM2 (F030 doesn't have it), so we use systick-monotonic to build a monotonic timer out of the SysTick instead. Also bumps up to defmt 0.3.
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‎.github/workflows/build_and_release.yml‎

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Original file line numberDiff line numberDiff line change
@@ -19,11 +19,24 @@ jobs:
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- name: Install flip-link
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run: cd / && cargo install flip-link
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- name: Build neotron-bmc-pico
23-
run: cd neotron-bmc-pico && cargo build --release --verbose --target=thumbv6m-none-eabi
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- name: Build neotron-bmc-pico for F030
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run: |
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cd neotron-bmc-pico
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cargo build --release --verbose --target=thumbv6m-none-eabi --features=stm32f030x6
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cd target/thumbv6m-none-eabi/release
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mv neotron-bmc-pico neotron-bmc-pico-f030
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- name: Build neotron-bmc-pico for F031
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run: |
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cd neotron-bmc-pico
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cargo build --release --verbose --target=thumbv6m-none-eabi --features=stm32f031
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cd target/thumbv6m-none-eabi/release
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mv neotron-bmc-pico neotron-bmc-pico-f031
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- name: Build neotron-bmc-nucleo
26-
run: cd neotron-bmc-nucleo && cargo build --release --verbose --target=thumbv7em-none-eabihf
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run: |
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cd neotron-bmc-nucleo
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cargo build --release --verbose --target=thumbv7em-none-eabihf
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- name: Get Branch Name
2942
if: github.event_name == 'push' && startswith(github.ref, 'refs/tags/')
@@ -48,7 +61,8 @@ jobs:
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uses: softprops/action-gh-release@v1
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with:
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files: |
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neotron-bmc-pico/target/thumbv6m-none-eabi/release/neotron-bmc
52-
neotron-bmc-nucleo/target/thumbv7em-none-eabihf/release/neotron-bmc
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neotron-bmc-pico/target/thumbv6m-none-eabi/release/neotron-bmc-pico-f030
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neotron-bmc-pico/target/thumbv6m-none-eabi/release/neotron-bmc-pico-f031
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neotron-bmc-nucleo/target/thumbv7em-none-eabihf/release/neotron-bmc-nucleo
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env:
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GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}

‎README.md‎

Lines changed: 6 additions & 85 deletions
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@@ -22,94 +22,15 @@ The NBMC appears to the main Neotron system processor as an Expansion Device. As
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### Neotron Pico
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25-
The NBMC firmware is designed to run on an ST Micro STM32F0 (STM32F031K6T6) microcontroller
26-
27-
* 32-bit Arm Cortex-M0+ Core
28-
* 3.3V I/O (5V tolerant)
29-
* 32 KiB Flash
30-
* 4 KiB SRAM
31-
* LQFP-32 package (0.8mm pitch)
32-
33-
34-
| Pin | Name | Signal | Function |
35-
| :--- | :--- | :---------- | :------------------------------------------- |
36-
| 02 | PF0 | BUTTON_nPWR | Power Button Input (active low) |
37-
| 03 | PF1 | BUTTON_nRST | Reset Button Input (active low) |
38-
| 06 | PA0 | MON_3V3 | 3.3V rail monitor Input (1.65V nominal) |
39-
| 07 | PA1 | MON_5V | 5.0V rail monitor Input (1.65V nominal) |
40-
| 08 | PA2 | nSYS_RESET | System Reset Output (active low) |
41-
| 09 | PA3 | DC_ON | PSU Enable Output (active high) |
42-
| 10 | PA4 | SPI1_nCS | SPI Chip Select Input (active low) |
43-
| 11 | PA5 | SPI1_SCK | SPI Clock Input |
44-
| 12 | PA6 | SPI1_CIPO | SPI Data Output |
45-
| 13 | PA7 | SPI1_COPI | SPI Data Input |
46-
| 14 | PB0 | LED0 | Output for Power LED |
47-
| 15 | PB1 | LED1 | Output for Status LED |
48-
| 18 | PA8 | IRQ_nHOST | Interrupt Output to the Host (active low) |
49-
| 19 | PA9 | USART1_TX | UART Transmit Output |
50-
| 20 | PA10 | USART1_RX | UART Receive Input |
51-
| 21 | PA11 | USART1_CTS | UART Clear-to-Send Output |
52-
| 22 | PA12 | USART1_RTS | UART Ready-to-Receive Input |
53-
| 23 | PA13 | SWDIO | SWD Progamming Data Input |
54-
| 24 | PA14 | SWCLK | SWD Programming Clock Input |
55-
| 25 | PA15 | PS2_CLK0 | Keyboard Clock Input |
56-
| 26 | PB3 | PS2_CLK1 | Mouse Clock Input |
57-
| 27 | PB4 | PS2_DAT0 | Keyboard Data Input |
58-
| 28 | PB5 | PS2_DAT1 | Mouse Data Input |
59-
| 29 | PB6 | I2C1_SCL | I²C Clock |
60-
| 30 | PB7 | I2C1_SDA | I²C Data |
61-
62-
Note that in the above table, the UART signals are wired as _Data Terminal Equipment (DTE)_ (i.e. like a PC, not like a Modem). Connect the NMBC *UART Transmit Output* pin to the *Input* pin of something like an FTDI TTL-232R-3V3 cable.
63-
64-
This design should also be pin-compatible with the following SoCs (although this firmware may need changes):
65-
66-
* STM32F042K4Tx
67-
* STM32F042K6Tx
68-
* STM32L071KBTx
69-
* STM32L071KZTx
70-
* STM32L072KZTx
71-
* STM32L081KZTx
72-
* STM32L082KZTx
73-
74-
Note that not all STM32 pins are 5V-tolerant, and the PS/2 protocol is a 5V open-collector system, so ensure that whichever part you pick has 5V-tolerant pins (marked `FT` or `FTt` in the datasheet) for the PS/2 signals. All of the parts above _should_ be OK, but they haven't been tested. Let us know if you try one!
25+
The NBMC firmware is designed to run on an ST Micro STM32F0 (STM32F031K6T6) microcontroller, as fitted to a [Neotron Pico](https://github.com/neotron-compute/neotron-pico).
26+
27+
See the [board-specific README](./neotron-bmc-pico/README.md)
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### Nucleo-F401
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78-
The NBMC also supports running on an ST Nucleo-F401RE, for development and debugging purposes. The STM32F401RET6U MCU has:
79-
80-
* 32-bit Arm Cortex-M4 Core
81-
* 3.3V I/O (5V tolerant)
82-
* 512 KiB Flash
83-
* 96 KiB SRAM
84-
* LQFP64 package (10 * 10 mm)
85-
86-
| CPU Pin | Nucleo-64 Pin | Name | Signal | Function |
87-
| ------- | ------------- | ---- | ----------- | ----------------------------------------- |
88-
| 2 | CN7 23 | PC13 | BUTTON_nPWR | Power Button Input (active low) |
89-
| 33 | CN10 16 | PB12 | BUTTON_nRST | Reset Button Input (active low) |
90-
| 34 | CN10 30 | PB13 | MON_3V3 | 3.3V rail monitor Input (1.65V nominal) |
91-
| 35 | CN10 28 | PB14 | MON_5V | 5.0V rail monitor Input (1.65V nominal) |
92-
| 36 | CN10 26 | PB15 | nSYS_RESET | System Reset Output (active low) |
93-
| 8 | CN8 6 | PC0 | DC_ON | PSU Enable Output (active high) |
94-
| 20 | CN8 3 | PA4 | SPI1_NSS | SPI Chip Select Input (active low) ?? |
95-
| 21 | CN5 6 | PA5 | SPI1_SCK | SPI Clock Input |
96-
| 22 | CN5 5 | PA6 | SPI1_MISO | SPI Data Output |
97-
| 23 | CN5 4 | PA7 | SPI1_MOSI | SPI Data Input |
98-
| 9 | CN6 5 | PC1 | POWER_LED | Output for Power LED |
99-
| 10 | CN7 35 | PC2 | STATUS_LED | Output for Status LED |
100-
| 11 | CN7 37 | PC3 | IRQ_nHOST | Interrupt Output to the Host (active low) |
101-
| 42 | CN10 21 | PA9 | USART1_TX | UART Transmit Output |
102-
| 43 | CN10 33 | PA10 | USART1_RX | UART Receive Input |
103-
| 44 | CN10 14 | PA11 | USART1_CTS | UART Clear-to-Send Output |
104-
| 45 | CN10 12 | PA12 | USART1_RTS | UART Ready-to-Receive Input |
105-
| 46 | CN7 13 | PA13 | SWDIO | SWD Progamming Data Input |
106-
| 49 | CN7 15 | PA14 | SWCLK | SWD Programming Clock Input |
107-
| 25 | CN10 6 | PC5 | PS2_CLK0 | Keyboard Clock Input |
108-
| 26 | CN8 4 | PB0 | PS2_CLK1 | Mouse Clock Input |
109-
| 27 | CN10 24 | PB1 | PS2_DAT0 | Keyboard Data Input |
110-
| 28 | CN10 22 | PB2 | PS2_DAT1 | Mouse Data Input |
111-
| 58 | CN10 17 | PB6 | I2C1_SCL | I²C Clock |
112-
| 59 | CN7 21 | PB7 | I2C1_SDA | I²C Data |
31+
The NBMC firmware can also run on an ST Micro STM32F4 Nucleo board.
32+
33+
See the [board-specific README](./neotron-bmc-nucleo/README.md)
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## SPI Communications Protocol
11536

‎neotron-bmc-nucleo/.cargo/config.toml‎

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@@ -10,7 +10,7 @@ rustflags = [
1010
]
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1212
[build]
13-
target = "thumbv7em-none-eabi" # Cortex-M0 and Cortex-M0+
13+
target = "thumbv7em-none-eabi" # Cortex-M4 and Cortex-M7
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1515
[alias]
1616
rb = "run --bin"

‎neotron-bmc-nucleo/README.md‎

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11
# Neotron-BMC-Nucleo
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33
## Introduction
4-
This folder is for Neotron BMC Nucleo.
5-
TODO: more details?
4+
5+
This folder is for the Board Management Controller (BMC) when running on an STM32F4 Nucleo board.
66

77
## Hardware Interface
8-
TODO: copy here from main Readme?
8+
9+
The NBMC also supports running on an ST Nucleo-F401RE, for development and debugging purposes. The STM32F401RET6U MCU has:
10+
11+
* 32-bit Arm Cortex-M4 Core
12+
* 3.3V I/O (5V tolerant)
13+
* 512 KiB Flash
14+
* 96 KiB SRAM
15+
* LQFP64 package (10 * 10 mm)
16+
17+
| CPU Pin | Nucleo-64 Pin | Name | Signal | Function |
18+
| ------- | ------------- | ---- | ----------- | ----------------------------------------- |
19+
| 2 | CN7 23 | PC13 | BUTTON_nPWR | Power Button Input (active low) |
20+
| 33 | CN10 16 | PB12 | BUTTON_nRST | Reset Button Input (active low) |
21+
| 34 | CN10 30 | PB13 | MON_3V3 | 3.3V rail monitor Input (1.65V nominal) |
22+
| 35 | CN10 28 | PB14 | MON_5V | 5.0V rail monitor Input (1.65V nominal) |
23+
| 36 | CN10 26 | PB15 | nSYS_RESET | System Reset Output (active low) |
24+
| 8 | CN8 6 | PC0 | DC_ON | PSU Enable Output (active high) |
25+
| 20 | CN8 3 | PA4 | SPI1_NSS | SPI Chip Select Input (active low) ?? |
26+
| 21 | CN5 6 | PA5 | SPI1_SCK | SPI Clock Input |
27+
| 22 | CN5 5 | PA6 | SPI1_MISO | SPI Data Output |
28+
| 23 | CN5 4 | PA7 | SPI1_MOSI | SPI Data Input |
29+
| 9 | CN6 5 | PC1 | POWER_LED | Output for Power LED |
30+
| 10 | CN7 35 | PC2 | STATUS_LED | Output for Status LED |
31+
| 11 | CN7 37 | PC3 | IRQ_nHOST | Interrupt Output to the Host (active low) |
32+
| 42 | CN10 21 | PA9 | USART1_TX | UART Transmit Output |
33+
| 43 | CN10 33 | PA10 | USART1_RX | UART Receive Input |
34+
| 44 | CN10 14 | PA11 | USART1_CTS | UART Clear-to-Send Output |
35+
| 45 | CN10 12 | PA12 | USART1_RTS | UART Ready-to-Receive Input |
36+
| 46 | CN7 13 | PA13 | SWDIO | SWD Progamming Data Input |
37+
| 49 | CN7 15 | PA14 | SWCLK | SWD Programming Clock Input |
38+
| 25 | CN10 6 | PC5 | PS2_CLK0 | Keyboard Clock Input |
39+
| 26 | CN8 4 | PB0 | PS2_CLK1 | Mouse Clock Input |
40+
| 27 | CN10 24 | PB1 | PS2_DAT0 | Keyboard Data Input |
41+
| 28 | CN10 22 | PB2 | PS2_DAT1 | Mouse Data Input |
42+
| 58 | CN10 17 | PB6 | I2C1_SCL | I²C Clock |
43+
| 59 | CN7 21 | PB7 | I2C1_SDA | I²C Data |
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1045
## Build Requirements
1146

‎neotron-bmc-pico/Cargo.toml‎

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@@ -1,30 +1,28 @@
11
[package]
22
authors = ["Jonathan 'theJPster' Pallant <[email protected]>"]
3-
name = "neotron-bmc"
3+
name = "neotron-bmc-pico"
44
edition = "2018"
55
version = "0.2.0"
66

77
[dependencies]
8-
cortex-m = "0.7.1"
9-
cortex-m-rt = "0.6.13"
10-
defmt = "0.2.0"
11-
defmt-rtt = "0.2.0"
8+
defmt = "0.3"
9+
cortex-m = { version = "0.7.5", features = ["inline-asm"] }
10+
defmt-rtt = "0.3"
1211
cortex-m-rtic = "1.0"
13-
panic-probe = { version = "0.2.0", features = ["print-defmt"] }
14-
# Use this line if you have an STM32F030K6T6
15-
# stm32f0xx-hal = { version = "0.17", features = ["stm32f030x6", "rt"] }
16-
# Use this line if you have an STM32F031K6T6
17-
stm32f0xx-hal = { version = "0.17", features = ["stm32f031", "rt"] }
12+
panic-probe = { version = "0.3.0", features = ["print-defmt"] }
13+
stm32f0xx-hal = { version = "0.18", features = ["rt"] }
1814
debouncr = "0.2"
1915
heapless= "0.7"
20-
fugit = "0.3"
16+
systick-monotonic = "1.0.0"
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2218
[features]
2319
# set logging levels here
2420
default = [
2521
"defmt-default",
26-
# "dependency-a/defmt-trace",
2722
]
23+
# You need to enable one of these two
24+
stm32f030x6 = [ "stm32f0xx-hal/stm32f030x6"]
25+
stm32f031 = [ "stm32f0xx-hal/stm32f031"]
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2927
# do NOT modify these features
3028
defmt-default = []

‎neotron-bmc-pico/README.md‎

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11
# Neotron-BMC-Pico
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33
## Introduction
4-
This folder is for Neotron BMC Pico.
5-
TODO: more details?
4+
5+
This folder is for the Board Management Controller (BMC) on a [Neotron Pico](https://github.com/neotron-compute/neotron-pico).
66

77
## Hardware Interface
8-
TODO: copy here from main Readme?
8+
9+
The NBMC firmware is designed to run on an ST Micro STM32F0 (STM32F031K6T6 or STM32F030K6T6) microcontroller
10+
11+
* 32-bit Arm Cortex-M0+ Core
12+
* 3.3V I/O (5V tolerant)
13+
* 32 KiB Flash
14+
* 4 KiB SRAM
15+
* LQFP-32 package (0.8mm pitch, 7mm x 7mm)
16+
17+
18+
| Pin | Name | Signal | Function |
19+
| :--- | :--- | :---------- | :------------------------------------------- |
20+
| 02 | PF0 | BUTTON_nPWR | Power Button Input (active low) |
21+
| 03 | PF1 | BUTTON_nRST | Reset Button Input (active low) |
22+
| 06 | PA0 | MON_3V3 | 3.3V rail monitor Input (1.65V nominal) |
23+
| 07 | PA1 | MON_5V | 5.0V rail monitor Input (1.65V nominal) |
24+
| 08 | PA2 | nSYS_RESET | System Reset Output (active low) |
25+
| 09 | PA3 | DC_ON | PSU Enable Output (active high) |
26+
| 10 | PA4 | SPI1_nCS | SPI Chip Select Input (active low) |
27+
| 11 | PA5 | SPI1_SCK | SPI Clock Input |
28+
| 12 | PA6 | SPI1_CIPO | SPI Data Output |
29+
| 13 | PA7 | SPI1_COPI | SPI Data Input |
30+
| 14 | PB0 | LED0 | Output for Power LED |
31+
| 15 | PB1 | LED1 | Output for Status LED |
32+
| 18 | PA8 | IRQ_nHOST | Interrupt Output to the Host (active low) |
33+
| 19 | PA9 | USART1_TX | UART Transmit Output |
34+
| 20 | PA10 | USART1_RX | UART Receive Input |
35+
| 21 | PA11 | USART1_CTS | UART Clear-to-Send Output |
36+
| 22 | PA12 | USART1_RTS | UART Ready-to-Receive Input |
37+
| 23 | PA13 | SWDIO | SWD Progamming Data Input |
38+
| 24 | PA14 | SWCLK | SWD Programming Clock Input |
39+
| 25 | PA15 | PS2_CLK0 | Keyboard Clock Input |
40+
| 26 | PB3 | PS2_CLK1 | Mouse Clock Input |
41+
| 27 | PB4 | PS2_DAT0 | Keyboard Data Input |
42+
| 28 | PB5 | PS2_DAT1 | Mouse Data Input |
43+
| 29 | PB6 | I2C1_SCL | I²C Clock |
44+
| 30 | PB7 | I2C1_SDA | I²C Data |
45+
46+
Note that in the above table, the UART signals are wired as _Data Terminal Equipment (DTE)_ (i.e. like a PC, not like a Modem). Connect the NMBC *UART Transmit Output* pin to the *Input* pin of something like an FTDI TTL-232R-3V3 cable.
47+
48+
This hardware design should also be pin-compatible with the following SoCs (although this firmware may need changes):
49+
50+
* STM32F042K4Tx
51+
* STM32F042K6Tx
52+
* STM32L071KBTx
53+
* STM32L071KZTx
54+
* STM32L072KZTx
55+
* STM32L081KZTx
56+
* STM32L082KZTx
57+
58+
Note that not all STM32 pins are 5V-tolerant, and the PS/2 protocol is a 5V open-collector system, so ensure that whichever part you pick has 5V-tolerant pins (marked `FT` or `FTt` in the datasheet) for the PS/2 signals. All of the parts above _should_ be OK, but they haven't been tested. Let us know if you try one!
959

1060
## Build Requirements
1161

@@ -14,12 +64,24 @@ TODO: copy here from main Readme?
1464
2. The `thumbv6m-none-eabi` target
1565
- run `rustup target add thumbv6m-none-eabi`
1666
3. `probe-run`
17-
- run `cargo install probe-run` from your `$HOME` dir (not this folder!)
67+
- run `cargo install probe-run`
1868
4. `flip-link`
19-
- run `cargo install flip-link` from your `$HOME` dir (not this folder!)
69+
- run `cargo install flip-link`
2070

21-
Then to build and flash, connect a probe supported by probe-rs (such as a SEGGER J-Link, or an ST-Link) and run:
71+
Then to build and flash for an STM32F031K6T6, connect a probe supported by probe-rs (such as a SEGGER J-Link, or an ST-Link) and run:
2272

2373
```
24-
$ cargo run --release
25-
```
74+
$ cargo run --release --features stm32f031
75+
```
76+
77+
For an STM32F030K6T6, run:
78+
79+
80+
```
81+
$ cargo run --release --features stm32f030x6
82+
```
83+
84+
## Licence
85+
86+
This source code as a whole is licensed under the GPL v3. Third-party crates are covered by their respective licences.
87+

‎neotron-bmc-pico/src/lib.rs‎

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@@ -6,8 +6,6 @@ use defmt_rtt as _; // global logger
66
use panic_probe as _;
77
use stm32f0xx_hal as _; // memory layout // panic handler
88

9-
pub mod monotonic;
10-
119
// same panicking *behavior* as `panic-probe` but doesn't print a panic message
1210
// this prevents the panic message being printed *twice* when `defmt::panic` is invoked
1311
#[defmt::panic_handler]

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