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Now works reliably at 2 MHz.
1 parent 38bfbdd commit 5c9446c

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2 files changed

+14
-11
lines changed

2 files changed

+14
-11
lines changed

neotron-bmc-pico/src/main.rs

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -446,6 +446,7 @@ mod app {
446446
Some(Message::SpiDisable) => {
447447
// Turn off the SPI peripheral. Don't need to check power state for this.
448448
ctx.shared.spi.lock(|s| s.stop());
449+
defmt::trace!("SPI Disable");
449450
}
450451
Some(Message::SpiRequest(req)) => {
451452
process_command(req, &mut register_state, |rsp| {

neotron-bmc-pico/src/spi.rs

Lines changed: 13 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -97,9 +97,11 @@ impl<const RXC: usize, const TXC: usize> SpiPeripheral<RXC, TXC> {
9797
// 3f. Disable DMA mode
9898
w.txdmaen().disabled();
9999
w.rxdmaen().disabled();
100-
// Extra: Turn on RX, TX and Error interrupts
100+
// Extra: Turn on RX and Error interrupts, but not TX. The TX
101+
// interrupt is turned off because we deliberately underflow the
102+
// FIFO during the receive phase of the transaction.
101103
w.rxneie().not_masked();
102-
w.txeie().not_masked();
104+
w.txeie().masked();
103105
w.errie().not_masked();
104106
w
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});
@@ -123,6 +125,14 @@ impl<const RXC: usize, const TXC: usize> SpiPeripheral<RXC, TXC> {
123125
let _ = spi.raw_read();
124126
}
125127

128+
// Enable the SPI device
129+
spi.stop();
130+
spi.dev.cr1.write(|w| {
131+
// Enable the peripheral
132+
w.spe().enabled();
133+
w
134+
});
135+
126136
spi
127137
}
128138

@@ -140,9 +150,6 @@ impl<const RXC: usize, const TXC: usize> SpiPeripheral<RXC, TXC> {
140150
w.ssi().slave_selected();
141151
w
142152
});
143-
// Load our dummy byte (our TX FIFO will send this then repeat it whilst
144-
// it underflows during the receive phase).
145-
self.raw_write(0xFF);
146153
}
147154

148155
/// Disable the SPI peripheral (i.e. when CS goes high)
@@ -187,10 +194,6 @@ impl<const RXC: usize, const TXC: usize> SpiPeripheral<RXC, TXC> {
187194

188195
pub fn handle_isr(&mut self) {
189196
let irq_status = self.dev.sr.read();
190-
if irq_status.fre().is_error() || irq_status.ovr().is_overrun() {
191-
// Handle errors!?
192-
defmt::info!("SPI sr=0b{:08b}", irq_status.bits());
193-
}
194197
if irq_status.rxne().is_not_empty() {
195198
self.rx_isr();
196199
}
@@ -218,8 +221,7 @@ impl<const RXC: usize, const TXC: usize> SpiPeripheral<RXC, TXC> {
218221
self.raw_write(next_tx);
219222
self.tx_idx += 1;
220223
} else {
221-
// No data - send padding
222-
self.raw_write(0xFF);
224+
// No data - send nothing
223225
}
224226
}
225227

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