Merge pull request #44 from Neotron-Compute/fix-reset

Force-reset the SPI block when you reset the host.

Author: thejpster

neotron-bmc-pico/src/main.rs

@@ -22,7 +22,7 @@ use stm32f0xx_hal::{
 	gpio::{Alternate, Floating, Input, Output, PullDown, PullUp, PushPull, AF1},
 	pac,
 	prelude::*,
-	serial,
+	rcc, serial,
 };
 
 use neotron_bmc_commands::Command;
@@ -163,6 +163,8 @@ mod app {
 		press_button_power_long: debouncr::Debouncer<u16, debouncr::Repeat16>,
 		/// Tracks reset button state for short presses. 75ms x 2 = 150ms is a long press
 		press_button_reset_short: debouncr::Debouncer<u8, debouncr::Repeat2>,
+		/// Run-time Clock Control (required for resetting peripheral blocks)
+		rcc: Option<rcc::Rcc>,
 	}
 
 	#[monotonic(binds = SysTick, default = true)]
@@ -342,6 +344,7 @@ mod app {
 			press_button_power_short: debouncr::debounce_2(false),
 			press_button_power_long: debouncr::debounce_16(false),
 			press_button_reset_short: debouncr::debounce_2(false),
+			rcc: Some(rcc),
 		};
 		let init = init::Monotonics(mono);
 		(shared_resources, local_resources, init)
@@ -350,14 +353,15 @@ mod app {
 	/// Our idle task.
 	///
 	/// This task is called when there is nothing else to do.
-	#[idle(shared = [msg_q_out, msg_q_in, spi, state_dc_power_enabled, pin_dc_on, pin_sys_reset])]
+	#[idle(shared = [msg_q_out, msg_q_in, spi, state_dc_power_enabled, pin_dc_on, pin_sys_reset], local = [rcc])]
 	fn idle(mut ctx: idle::Context) -> ! {
 		// TODO: Get this from the VERSION static variable or from PKG_VERSION
 		let mut register_state = RegisterState {
 			firmware_version: *b"Neotron BMC v0.4.1-alpha\x00\x00\x00\x00\x00\x00\x00\x00",
 			..Default::default()
 		};
-
+		// Take this out of the `local` object to avoid sharing issues.
+		let mut rcc = ctx.local.rcc.take().unwrap();
 		defmt::info!("Idle is running...");
 		loop {
 			match ctx.shared.msg_q_out.dequeue() {
@@ -430,6 +434,7 @@ mod app {
 					if ctx.shared.state_dc_power_enabled.lock(|r| *r) == DcPowerState::On {
 						defmt::info!("Reset!");
 						ctx.shared.pin_sys_reset.lock(|pin| pin.set_low().unwrap());
+						ctx.shared.spi.lock(|s| s.reset(&mut rcc));
 						// Returns an error if it's already scheduled (but we don't care)
 						let _ = exit_reset::spawn_after(RESET_DURATION_MS.millis());
 					}

neotron-bmc-pico/src/spi.rs

@@ -6,6 +6,7 @@
 use stm32f0xx_hal::{pac, prelude::*, rcc::Rcc};
 
 pub struct SpiPeripheral<const RXC: usize, const TXC: usize> {
+	/// Our PAC object for register access
 	dev: pac::SPI1,
 	/// A space for bytes received from the host
 	rx_buffer: [u8; RXC],
@@ -23,6 +24,9 @@ pub struct SpiPeripheral<const RXC: usize, const TXC: usize> {
 }
 
 impl<const RXC: usize, const TXC: usize> SpiPeripheral<RXC, TXC> {
+	const MODE: embedded_hal::spi::Mode = embedded_hal::spi::MODE_0;
+
+	/// Construct a new driver
 	pub fn new<SCKPIN, MISOPIN, MOSIPIN>(
 		dev: pac::SPI1,
 		pins: (SCKPIN, MISOPIN, MOSIPIN),
@@ -35,24 +39,53 @@ impl<const RXC: usize, const TXC: usize> SpiPeripheral<RXC, TXC> {
 	{
 		defmt::info!("pclk = {}", rcc.clocks.pclk().0,);
 
-		let mode = embedded_hal::spi::MODE_0;
-
 		// Set SPI up in Controller mode. This will cause the HAL to enable the clocks and power to the IP block.
 		// It also checks the pins are OK.
-		let spi_controller = stm32f0xx_hal::spi::Spi::spi1(dev, pins, mode, 8_000_000u32.hz(), rcc);
+		let spi_controller =
+			stm32f0xx_hal::spi::Spi::spi1(dev, pins, Self::MODE, 8_000_000u32.hz(), rcc);
 		// Now disassemble the driver so we can set it into Controller mode instead
 		let (dev, _pins) = spi_controller.release();
 
+		let mut spi = SpiPeripheral {
+			dev,
+			rx_buffer: [0u8; RXC],
+			rx_idx: 0,
+			tx_buffer: [0u8; TXC],
+			tx_idx: 0,
+			tx_ready: 0,
+			is_done: false,
+		};
+
+		spi.config(Self::MODE);
+
+		// Empty the receive register
+		while spi.has_rx_data() {
+			let _ = spi.raw_read();
+		}
+
+		// Enable the SPI device
+		spi.stop();
+		spi.dev.cr1.write(|w| {
+			// Enable the peripheral
+			w.spe().enabled();
+			w
+		});
+
+		spi
+	}
+
+	/// Set up the registers
+	fn config(&mut self, mode: embedded_hal::spi::Mode) {
 		// We are following DM00043574, Section 30.5.1 Configuration of SPI
 
 		// 1. Disable SPI
-		dev.cr1.modify(|_r, w| {
+		self.dev.cr1.modify(|_r, w| {
 			w.spe().disabled();
 			w
 		});
 
 		// 2. Write to the SPI_CR1 register. Apologies for the outdated terminology.
-		dev.cr1.write(|w| {
+		self.dev.cr1.write(|w| {
 			// 2a. Configure the serial clock baud rate (ignored in peripheral mode)
 			w.br().div2();
 			// 2b. Configure the CPHA and CPOL bits.
@@ -83,7 +116,7 @@ impl<const RXC: usize, const TXC: usize> SpiPeripheral<RXC, TXC> {
 		});
 
 		// 3. Write to SPI_CR2 register
-		dev.cr2.write(|w| {
+		self.dev.cr2.write(|w| {
 			// 3a. Configure the DS[3:0] bits to select the data length for the transfer (0b111 = 8-bit words).
 			unsafe { w.ds().bits(0b111) };
 			// 3b. Disable hard-output on the CS pin (ignored in Master mode)
@@ -109,31 +142,6 @@ impl<const RXC: usize, const TXC: usize> SpiPeripheral<RXC, TXC> {
 		// 4. SPI_CRCPR - not required
 
 		// 5. DMA registers - not required
-
-		let mut spi = SpiPeripheral {
-			dev,
-			rx_buffer: [0u8; RXC],
-			rx_idx: 0,
-			tx_buffer: [0u8; TXC],
-			tx_idx: 0,
-			tx_ready: 0,
-			is_done: false,
-		};
-
-		// Empty the receive register
-		while spi.has_rx_data() {
-			let _ = spi.raw_read();
-		}
-
-		// Enable the SPI device
-		spi.stop();
-		spi.dev.cr1.write(|w| {
-			// Enable the peripheral
-			w.spe().enabled();
-			w
-		});
-
-		spi
 	}
 
 	/// Enable the SPI peripheral (i.e. when CS goes low)
@@ -160,6 +168,41 @@ impl<const RXC: usize, const TXC: usize> SpiPeripheral<RXC, TXC> {
 		});
 	}
 
+	/// Fully reset the SPI peripheral
+	pub fn reset(&mut self, _rcc: &mut stm32f0xx_hal::rcc::Rcc) {
+		self.dev.cr1.write(|w| {
+			// Disable the peripheral
+			w.spe().disabled();
+			w
+		});
+
+		// Reset the IP manually. This is OK as we have exclusive access to the
+		// RCC peripheral. But sadly the RCC peripheral doesn't let us reset
+		// anything (it assumes it can handle it all internally).
+		let reset_reg = 0x4002_100C as *mut u32;
+		let spi1_bit = 1 << 12;
+		unsafe {
+			*reset_reg |= spi1_bit;
+			*reset_reg &= !(spi1_bit);
+		}
+
+		// Reconfigure
+		self.config(Self::MODE);
+
+		// Empty the receive register
+		while self.has_rx_data() {
+			let _ = self.raw_read();
+		}
+
+		// Enable the SPI device and leave it idle
+		self.stop();
+		self.dev.cr1.write(|w| {
+			// Enable the peripheral
+			w.spe().enabled();
+			w
+		});
+	}
+
 	/// Does the RX FIFO have any data in it?
 	fn has_rx_data(&self) -> bool {
 		self.dev.sr.read().rxne().is_not_empty()