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thejpsterthejpster
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Basic boot skeleton.
Can be booted by the Neotron 32 BIOS. I do need to think of a nicer way of handling systems with different amounts of memory, and also to ensure global variables are initialised correctly.
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‎.cargo/config‎

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[target.thumbv7em-none-eabihf]
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runner = 'arm-none-eabi-gdb --command=gdb.cfg -w'
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rustflags = [
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"-C", "link-arg=-Tneotron-os-26k.ld",
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]
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[build]
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target = "thumbv7em-none-eabihf"

‎.gitignore‎

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/target
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**/*.rs.bk
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Cargo.lock

‎.gitmodules‎

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[submodule "common"]
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path = common
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url = ../Neotron-Common-BIOS.git

‎Cargo.toml‎

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[package]
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name = "neotron_os"
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version = "0.1.0"
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authors = ["Jonathan 'theJPster' Pallant <[email protected]>"]
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edition = "2018"
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description = "The Neotron Operating System"
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license = "GPL-3.0-or-later"
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readme = "README.md"
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repository = "https://github.com/neotron-compute/Neotron-OS"
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[[bin]]
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name = "neotron_os"
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test = false
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bench = false
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[profile.release]
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lto = true
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debug = true
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codegen-units = 1
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opt-level = "s"
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[dependencies.neotron_common_bios]
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path = "./common"

‎LICENSE.md‎

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‎common‎

Submodule common added at 10e6ce2

‎gdb.cfg‎

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target extended-remote :3333
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# print demangled symbols by default
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set print asm-demangle on
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monitor arm semihosting enable
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# # send captured ITM to the file itm.fifo
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# # (the microcontroller SWO pin must be connected to the programmer SWO pin)
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# # 8000000 must match the core clock frequency
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# monitor tpiu config internal itm.fifo uart off 8000000
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# # OR: make the microcontroller SWO pin output compatible with UART (8N1)
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# # 2000000 is the frequency of the SWO pin
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# monitor tpiu config external uart off 8000000 2000000
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# # enable ITM port 0
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# monitor itm port 0 on
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load
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step
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continue
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‎neotron-os-26k.ld‎

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/* # Developer notes
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- Symbols that start with a double underscore (__) are considered "private"
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- Symbols that start with a single underscore (_) are considered "semi-public"; they can be
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overridden in a user linker script, but should not be referred from user code (e.g. `extern "C" {
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static mut __sbss }`).
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- `EXTERN` forces the linker to keep a symbol in the final binary. We use this to make sure a
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symbol if not dropped if it appears in or near the front of the linker arguments and "it's not
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needed" by any of the preceding objects (linker arguments)
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- `PROVIDE` is used to provide default values that can be overridden by a user linker script
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- On alignment: it's important for correctness that the VMA boundaries of both .bss and .data *and*
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the LMA of .data are all 4-byte aligned. These alignments are assumed by the RAM initialization
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routine. There's also a second benefit: 4-byte aligned boundaries means that you won't see
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"Address (..) is out of bounds" in the disassembly produced by `objdump`.
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*/
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/* Provides information about the memory layout of the device */
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MEMORY
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{
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/* The OS gets the top 128 KiB of Flash, leaving the first 128 KiB for the BIOS */
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FLASH (rx) : ORIGIN = 0x00020000, LENGTH = 128K
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/* The BIOS gets the top 6 KiB of SRAM (including the Stack), leaving 26 KiB for the OS (at 0x2000_0000 to 0x2000_67FF) */
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RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 26K
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}
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/* # Entry point = what the BIOS calls to start the OS */
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ENTRY(entry_point);
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EXTERN(__RESET_VECTOR);
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/* # Sections */
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SECTIONS
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{
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/* ## Sections in FLASH */
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.entry_point ORIGIN(FLASH) :
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{
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KEEP(*(.entry_point))
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} > FLASH
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PROVIDE(_stext = ADDR(.entry_point) + SIZEOF(.entry_point));
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/* ### .text */
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.text _stext :
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{
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*(.text .text.*);
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*(.HardFaultTrampoline);
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*(.HardFault.*);
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} > FLASH
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/* ### .rodata */
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.rodata : ALIGN(4)
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{
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*(.rodata .rodata.*);
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/* 4-byte align the end (VMA) of this section.
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This is required by LLD to ensure the LMA of the following .data
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section will have the correct alignment. */
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. = ALIGN(4);
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} > FLASH
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/* ## Sections in RAM */
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/* ### .data */
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.data : ALIGN(4)
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{
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. = ALIGN(4);
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__sdata = .;
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*(.data .data.*);
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. = ALIGN(4); /* 4-byte align the end (VMA) of this section */
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__edata = .;
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} > RAM AT > FLASH
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/* LMA of .data */
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__sidata = LOADADDR(.data);
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/* ### .bss */
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.bss : ALIGN(4)
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{
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. = ALIGN(4);
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__sbss = .;
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*(.bss .bss.*);
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. = ALIGN(4); /* 4-byte align the end (VMA) of this section */
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__ebss = .;
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} > RAM
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/* ### .uninit */
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.uninit (NOLOAD) : ALIGN(4)
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{
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. = ALIGN(4);
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*(.uninit .uninit.*);
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. = ALIGN(4);
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} > RAM
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/* Place the heap right after `.uninit` */
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. = ALIGN(4);
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__sheap = .;
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/* ## .got */
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/* Dynamic relocations are unsupported. This section is only used to detect relocatable code in
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the input files and raise an error if relocatable code is found */
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.got (NOLOAD) :
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{
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KEEP(*(.got .got.*));
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}
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/* ## Discarded sections */
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/DISCARD/ :
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{
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/* Unused exception related info that only wastes space */
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*(.ARM.exidx);
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*(.ARM.exidx.*);
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*(.ARM.extab.*);
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}
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}
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/* Do not exceed this mark in the error messages below | */
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/* # Alignment checks */
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ASSERT(ORIGIN(FLASH) % 4 == 0, "
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ERROR(cortex-m-rt): the start of the FLASH region must be 4-byte aligned");
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ASSERT(ORIGIN(RAM) % 4 == 0, "
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ERROR(cortex-m-rt): the start of the RAM region must be 4-byte aligned");
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ASSERT(__sdata % 4 == 0 && __edata % 4 == 0, "
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BUG(cortex-m-rt): .data is not 4-byte aligned");
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ASSERT(__sidata % 4 == 0, "
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BUG(cortex-m-rt): the LMA of .data is not 4-byte aligned");
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ASSERT(__sbss % 4 == 0 && __ebss % 4 == 0, "
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BUG(cortex-m-rt): .bss is not 4-byte aligned");
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ASSERT(__sheap % 4 == 0, "
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BUG(cortex-m-rt): start of .heap is not 4-byte aligned");
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/* # Position checks */
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/* ## .text */
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ASSERT(_stext + SIZEOF(.text) < ORIGIN(FLASH) + LENGTH(FLASH), "
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ERROR(cortex-m-rt): The .text section must be placed inside the FLASH memory.
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Set _stext to an address smaller than 'ORIGIN(FLASH) + LENGTH(FLASH)'");
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/* # Other checks */
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ASSERT(SIZEOF(.got) == 0, "
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ERROR(cortex-m-rt): .got section detected in the input object files
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Dynamic relocations are not supported. If you are linking to C code compiled using
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the 'cc' crate then modify your build script to compile the C code _without_
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the -fPIC flag. See the documentation of the `cc::Build.pic` method for details.");
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/* Do not exceed this mark in the error messages above | */

‎src/main.rs‎

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//! # The Neotron Operating System
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//!
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//! This OS is intended to be loaded by a Neotron BIOS.
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#![no_std]
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#![no_main]
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use core::fmt::Write;
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use neotron_common_bios as common;
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#[link_section = ".entry_point"]
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#[no_mangle]
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#[used]
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pub static ENTRY_POINT: extern "C" fn(&'static common::Api) -> ! = entry_point;
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static mut API: Option<&'static common::Api> = None;
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struct SerialConsole;
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impl core::fmt::Write for SerialConsole {
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fn write_str(&mut self, data: &str) -> core::fmt::Result {
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if let Some(api) = unsafe { API } {
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let _res = (api.serial_write)(
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0,
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common::ApiByteSlice::new(data.as_bytes()),
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common::Option::None,
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);
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}
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Ok(())
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}
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}
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#[no_mangle]
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extern "C" fn entry_point(api: &'static common::Api) -> ! {
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unsafe {
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API = Some(api);
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}
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writeln!(SerialConsole, "Neotron OS.").unwrap();
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writeln!(SerialConsole, "BIOS Version: {}", (api.bios_version_get)()).unwrap();
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writeln!(
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SerialConsole,
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"BIOS API Version: {}",
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(api.api_version_get)()
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)
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.unwrap();
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loop {
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for _ in 0..80_000_000 {
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let _ = (api.api_version_get)();
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}
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writeln!(SerialConsole, "tick...").unwrap();
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}
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}
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#[inline(never)]
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#[panic_handler]
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fn panic(_info: &core::panic::PanicInfo) -> ! {
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use core::sync::atomic::{self, Ordering};
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loop {
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atomic::compiler_fence(Ordering::SeqCst);
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}
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}

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