Re-arranged memory.

BIOS is at the top of the 256 KB block of RAM. Application is at the bottom. Core 0 and Core 1 stacks get the upper two
4KB blocks.

Author: thejpster

Cargo.toml

@@ -11,7 +11,7 @@ version = "0.2.0"
 # Useful Cortex-M specific functions (e.g. SysTick)
 cortex-m = "0.7"
 # The Raspberry Pi Pico HAL
-pico = { git = "https://github.com/rp-rs/rp-hal.git" }
+rp-pico = "0.3"
 # Cortex-M run-time (or start-up) code
 cortex-m-rt = "0.7"
 # The BIOS API we export to the OS
@@ -28,12 +28,12 @@ defmt = "0.3"
 defmt-rtt = "0.3"
 # Send panics to the debugger
 panic-probe = "0.2"
-# Fetches the BIOS version from git
+# Fetches git hashes from git at compile time
 git-version = "0.3"
-# RP2040 PIO driver
-pio = { git = "https://github.com/rp-rs/pio-rs.git", branch = "main" }
-# RP2040 PIO driver macros
-pio-proc = { git = "https://github.com/rp-rs/pio-rs.git", branch = "main" }
+# RP2040 PIO assembler
+pio = "0.2"
+# Macros for RP2040 PIO assembler
+pio-proc = "0.2"
 
 [features]
 default = [

README.md

@@ -47,18 +47,18 @@ The Neotron BIOS uses the [defmt](https://crates.io/crates/defmt) crate to provi
 
 2. Flash your *Debugger* Pico with https://github.com/majbthrd/DapperMime firmware (e.g. by copying the UF2 file to the USB Mass Storage device)
 
-3. On your PC, install *probe-rs-rp* from the RP2040-specific [probe-run](https://github.com/knurling-rs/probe-run) fork at https://github.com/rp-rs/probe-run.
+3. On your PC, install [*probe-rs*](https://github.com/knurling-rs/probe-run), the programming tool from [Ferrous System's](https://www.ferrous-systems.com) [Knurling Project](https://github.com/knurling).
 
 ```console
-user@host ~ $ cargo install probe-rs-rp
+user@host ~ $ cargo install probe-rs
 ```
 
 4. Power on your Neotron Pico.
 
-5. Build and load the Neotron BIOS, and view the debug output stream, with `cargo run`:
+5. Build and load the Neotron BIOS, and view the debug output stream, with `cargo run --release`:
 
 ```console
-user@host ~/neotron-pico-bios $ cargo run --release
+user@host ~/neotron-pico-bios $ DEFMT_LOG=debug cargo run --release
    Compiling neotron-pico-bios v0.1.0 (/home/jonathan/Documents/neotron/neotron-pico-bios)
     Finished release [optimized + debuginfo] target(s) in 0.76s
      Running `probe-run-rp --chip RP2040 target/thumbv6m-none-eabi/release/neotron-pico-bios`
@@ -75,6 +75,8 @@ user@host ~/neotron-pico-bios $ cargo run --release
 └─ neotron_pico_bios::__cortex_m_rt_main @ src/main.rs:128
 ``` 
 
+You should see your Neotron Pico boot, both over RTT in the `probe-run` output, and also on the VGA output.
+
 ## Changelog
 
 See [CHANGELOG.md](./CHANGELOG.md)

memory.x

@@ -21,23 +21,46 @@ MEMORY {
     /*
      * This is the remainder of the 2048 KiB flash chip.
      */
-    FLASH_OS: ORIGIN = 0x10020000, LENGTH = 2048K - 128K
+    FLASH_OS : ORIGIN = 0x10020000, LENGTH = 2048K - 128K
     /*
-     * This is the internal SRAM in the RP2040.
+     * This is the bottom of the four striped banks of SRAM in the RP2040.
      */
-    RAM   : ORIGIN = 0x20000000, LENGTH = 256K
+    RAM_OS : ORIGIN = 0x20000000, LENGTH = 0x3C000
+    /*
+     * This is the top of the four striped banks of SRAM in the RP2040.
+     */
+    RAM : ORIGIN = 0x2003C000, LENGTH = 16K
+    /*
+     * This is the fifth bank, a 4KB block. We use this for Core 0 Stack.
+     */
+    RAM_CORE0_STACK : ORIGIN = 0x20040000, LENGTH = 4K
+    /*
+     * This is the sixth bank, a 4KB block. We use this for Core 1 Stack.
+     */
+    RAM_CORE1_STACK : ORIGIN = 0x20041000, LENGTH = 4K
 }
-/* This is where the call stack will be allocated. */
-/* The stack is of the full descending type. */
-/* You may want to use this variable to locate the call stack and static
-   variables in different memory regions. Below is shown the default value */
-_stack_start = ORIGIN(RAM) + LENGTH(RAM);
+
+/*
+ * This is where the call stack for Core 0 will be located. The stack is of
+ * the full descending type. You may want to use this variable to locate the
+ * call stack and static variables in different memory regions. Below is
+ * shown the default value
+ */
+_stack_start = ORIGIN(RAM_CORE0_STACK) + LENGTH(RAM_CORE0_STACK);
+
+/*
+ * This is where the call stack for Core 1 will be located.
+ */
+_core1_stack_bottom = ORIGIN(RAM_CORE1_STACK);
+_core1_stack_len = LENGTH(RAM_CORE1_STACK);
 
 /*
  * Export some symbols to tell the BIOS where it might find the OS.
  */
 _flash_os_start = ORIGIN(FLASH_OS);
 _flash_os_len = LENGTH(FLASH_OS);
+_ram_os_start = ORIGIN(RAM_OS);
+_ram_os_len = LENGTH(RAM_OS);
 
 SECTIONS {
     /* ### RP2040 Boot loader */

src/main.rs

@@ -44,13 +44,13 @@ pub mod vga;
 // -----------------------------------------------------------------------------
 
 use cortex_m_rt::entry;
-use defmt::*;
+use defmt::info;
 use defmt_rtt as _;
 use embedded_hal::digital::v2::OutputPin;
 use embedded_time::rate::*;
 use git_version::git_version;
 use panic_probe as _;
-use pico::{
+use rp_pico::{
 	self,
 	hal::{
 		self,
@@ -68,16 +68,6 @@ use pico::{
 // Static and Const Data
 // -----------------------------------------------------------------------------
 
-/// This is the standard RP2040 bootloader. It must be stored in the first 256
-/// bytes of the external SPI Flash chip. It will map the external SPI flash
-/// chip to address `0x1000_0000` and jump to an Interrupt Vector Table at
-/// address `0x1000_0100` (i.e. immediately after the bootloader).
-///
-/// See `memory.x` for a definition of the `.boot2` section.
-#[link_section = ".boot2"]
-#[used]
-pub static BOOT2: [u8; 256] = rp2040_boot2::BOOT_LOADER_W25Q080;
-
 /// BIOS version
 const GIT_VERSION: &str = git_version!();
 
@@ -88,7 +78,10 @@ static TEXT_CONSOLE: vga::TextConsole = vga::TextConsole::new();
 // Functions
 // -----------------------------------------------------------------------------
 
-/// Prints to the screen
+/// Prints to the screen.
+///
+/// This function is NOT interrupt safe. Only call from the main thread, on
+/// core 1.
 #[macro_export]
 macro_rules! print {
     ($($arg:tt)*) => {
@@ -99,7 +92,10 @@ macro_rules! print {
     };
 }
 
-/// Prints to the screen and puts a new-line on the end
+/// Prints to the screen and puts a new-line on the end.
+///
+/// This function is NOT interrupt safe. Only call from the main thread, on
+/// core 1.
 #[macro_export]
 macro_rules! println {
     () => (print!("\n"));
@@ -136,12 +132,12 @@ fn main() -> ! {
 
 	// Run at 126 MHz SYS_PLL, 48 MHz, USB_PLL
 
-	let xosc = hal::xosc::setup_xosc_blocking(pac.XOSC, pico::XOSC_CRYSTAL_FREQ.Hz())
+	let xosc = hal::xosc::setup_xosc_blocking(pac.XOSC, rp_pico::XOSC_CRYSTAL_FREQ.Hz())
 		.map_err(|_x| false)
 		.unwrap();
 
 	// Configure watchdog tick generation to tick over every microsecond
-	watchdog.enable_tick_generation((pico::XOSC_CRYSTAL_FREQ / 1_000_000) as u8);
+	watchdog.enable_tick_generation((rp_pico::XOSC_CRYSTAL_FREQ / 1_000_000) as u8);
 
 	let mut clocks = hal::clocks::ClocksManager::new(pac.CLOCKS);
 
@@ -183,7 +179,7 @@ fn main() -> ! {
 	let mut sio = hal::sio::Sio::new(pac.SIO);
 
 	// Configure and grab all the RP2040 pins the Pico exposes.
-	let pins = pico::Pins::new(
+	let pins = rp_pico::Pins::new(
 		pac.IO_BANK0,
 		pac.PADS_BANK0,
 		sio.gpio_bank0,
@@ -223,11 +219,57 @@ fn main() -> ! {
 
 	TEXT_CONSOLE.set_text_buffer(unsafe { &mut vga::CHAR_ARRAY });
 
-	info!("VGA intialised");
+	for _col in 0..vga::NUM_TEXT_ROWS {
+		println!();
+	}
+
+	TEXT_CONSOLE.move_to(0, 0);
+
+	println!("Neotron Pico BIOS, for the Raspberry Pi RP2040");
+	println!("Copyright © Jonathan 'theJPster' Pallant and the Neotron Developers, 2021");
+	println!("Version {}", GIT_VERSION);
+	println!();
+	println!("This program is free software: you can redistribute it and/or modify");
+	println!("it under the terms of the GNU General Public License as published by");
+	println!("the Free Software Foundation, either version 3 of the License, or");
+	println!("(at your option) any later version.");
+	println!();
+	println!("This program is distributed in the hope that it will be useful,");
+	println!("but WITHOUT ANY WARRANTY; without even the implied warranty of");
+	println!("MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the");
+	println!("GNU General Public License for more details.");
+	println!();
+	println!("You should have received a copy of the GNU General Public License");
+	println!("along with this program.  If not, see https://www.gnu.org/licenses/.");
+	println!();
+	println!("Searching for Neotron OS...");
+
+	extern "C" {
+		static mut _flash_os_start: u32;
+		static mut _flash_os_len: u32;
+		static mut _ram_os_start: u32;
+		static mut _ram_os_len: u32;
+	}
+
+	let flash_os_start = unsafe {
+		&mut _flash_os_start as *mut u32 as usize
+	};
+	let flash_os_len = unsafe {
+		&mut _flash_os_len as *mut u32 as usize
+	};
+	let ram_os_start = unsafe {
+		&mut _ram_os_start as *mut u32 as usize
+	};
+	let ram_os_len = unsafe {
+		&mut _ram_os_len as *mut u32 as usize
+	};
+
+	println!("OS Flash is {:08x}, {} bytes", flash_os_start, flash_os_len);
+	println!("OS RAM is {:08x}, {} bytes", ram_os_start, ram_os_len);
 
 	let mut x: u32 = 0;
 	loop {
-		println!("x = {}", x);
+		print!("\rx = {}", x);
 		x = x.wrapping_add(1);
 	}
 }