NetFPGA 10G RLDRAM Stream
RLDRAM Stream contrib_projects.
This page is under construction.
After cloning NetFPGA10G-live, follow below steps to set up environments for RLDRAM projects.
-
Download Xilinx RLDRAM memory controller to ./contrib-projects/rldram_stream/hw/pcores/nf10_rldram_stream_v1_00_a/hdl/verilog/.
-
Extract the downloaded file at the same directory.
-
Create a directory xilinx, copy all verilog files in ./XAPP852/verilog/ to xilinx directory.
-
Do a Make outside the xilinx directory, to patch the files for our design requirements.