Green Reference Router

Green Reference Router

Project Summary

Status :Released

Version : 1.0

Authors : ***

NetFPGA base source : 2.0

1. 1. The Green Reference Router

The Green Reference Router is a project built on top of Reference Router in order to design a "Green Router": an energy aware router. The Reference Router provides a hardware register which allows the board to switch the clock frequency between 62.5 MHz and 125 MHz. However, the original Reference Router does not allow this change at run-time and when the clock frequency is changed the board needs to update all the ARP (Address Resolution Protocol), routing tables and other important run-time data taking several seconds.

1. 1. 1. Run-time Frequency Switch

We have improved such a functionality providing a software module (called "Download Very Fast", you can find it as "download_very_fast.c" inside the "sw" sub-directory of the green_reference_router project) which save the state of the board before restarting the board with the new clock frequency with the last previous board state. With this new functionality, the boards takes 2ms to switch the clock frequency. (Obviously, this reset time δ results in a QoS decrease; in particular it may cause loss of the incoming packets). From the energy point of view, we have assessed that the energy necessary to apply our switching procedure is negligible. Using this new facility we have built, the frequency switch can be performed at run-time, giving us the possibility to design a new green architecture, with frequency scaling capabilities.

1. 1. 1. Green Reference Router: Verilog Architecture

We have also introduced a three hardware modules inside the User Data Path Pipeline, which are used to measure at hardware level the input and output bit rate and a software module, called Governor, implements a Control Policy to switch the clock according to the bit rate to be processed. The resulting architecture is depicted in Figure 9. The green boxes indicate the new modules whereas the blue boxes refer to the original design. 

1. 1. 1. Hardware modules to measure the input and the output bit rate
         1. Input Bit Rate Calculator

The Input Bit Rate Calculator is a hardware module that provides the input bit rate which is received within the input queues from the Ethernet ports. This module computes and gives the input bit rate of each queue and the overall bit rate. Information needed to compute the input bit rate is already available within the NetFPGA registers. In particular, the number of bytes received in each input queue is accessible through the MAC_GRP_i_RX_QUEUE_NUM_BYTES_PUSHED_REG register (where i ranges in {0, …, 3} as we have four input queues). Each of the four registers contains the progressive number of bytes received in the corresponding input queue. Each register has a fixed dimension of 32 bits: when the value of the register reaches the maximum it restarts from 0. In order to compute the bit rate for the input queue i we need to read the value of the ith register each time window w and convert the number of received bytes within w in a bit rate value. In the following, a list of new defined registers to provide the bit rate to the software level.

Register Name Description INPUT_CYCLE Input register containing the time information for sampling INPUT_Q0_BITRATE Output register containing bit rate for queue 0 INPUT_Q1_BITRATE Output register containing bit rate for queue 1 INPUT_Q2_BITRATE Output register containing bit rate for queue 2 INPUT_Q3_BITRATE Output register containing bit rate for queue 3 TOTAL_INPUT_BITRATE Output register containing the total bit rate

1. 1. 1. 1. Output Bit Rate Calculator

Similarly to the Input Bit Rate Calculator module, the Output Bitrate Calculator is a hardware module that provides the output bit rate for each Tx queue and the overall output bit rate as well. The same concepts discussed before are applied even in this case. Moreover, the same number of registers have been defined for the output bit rate and have a similar purpose. The Output Bit Rate Calculator module receives a signal from each of the MAC output queues. This signal has the same value corresponding to the MAC_GRP_i_TX_QUEUE_NUM_BYTES_PUSHED_REG registers for i = {0, . . . , 3}. It counts the number of bytes that have been sent out of the Tx queues to Ethernet. We have slightly changed the nf2_core.v, mac_grp_regs.v, and nf2_mac_grp.v modules in order to forward the reg_file[MAC_GRP_TX_QUEUE_NUM_BYTES_PUSHED] signal to the User Data Path module. Therefore, defining the Output Bit Rate Calculator module within the User Data Path allowed us to capture the signals above and process them. Then we have proceeded analogously to Section 3.1 using a similar state machine architecture.