@@ -689,7 +689,6 @@ def read_rhd(filename, file_format: str):
689689 data_dtype [1 ] = "uint16"
690690
691691
692-
693692 # 2: RHD2000 supply voltage channel
694693 for chan_info in channels_by_type [2 ]:
695694 name = chan_info ["custom_channel_name" ]
@@ -744,7 +743,11 @@ def read_rhd(filename, file_format: str):
744743 if len (channels_by_type [sig_type ]) > 0 :
745744 name = {4 : "DIGITAL-IN" , 5 : "DIGITAL-OUT" }[sig_type ]
746745 chan_info = channels_by_type [sig_type ][0 ]
747- chan_info ["custom_channel_name" ] = name # overwite to allow memmap to work
746+ # So currently until we have get_digitalsignal_chunk we need to do a tiny hack to
747+ # make this memory map work correctly. So since our digital data is not organized
748+ # by channel like analog/ADC are we have to overwrite the native name to create
749+ # a single permanent name that we can find with channel id
750+ chan_info ["native_channel_name" ] = name # overwite to allow memmap to work
748751 chan_info ["sampling_rate" ] = sr
749752 chan_info ["units" ] = "TTL" # arbitrary units TTL for logic
750753 chan_info ["gain" ] = 1.0
@@ -755,10 +758,12 @@ def read_rhd(filename, file_format: str):
755758 else :
756759 data_dtype [sig_type ] = "uint16"
757760
758- if bool (global_info ["notch_filter_mode" ]) and version >= V ("3.0" ):
759- global_info ["notch_filter_applied" ] = True
761+ if global_info ["notch_filter_mode" ] == 2 and version >= V ("3.0" ):
762+ global_info ["notch_filter" ] = '60Hz'
763+ elif global_info ["notch_filter_mode" ] == 1 and version >= V ("3.0" ):
764+ global_info ["notch_filter" ] = '50Hz'
760765 else :
761- global_info ["notch_filter_applied " ] = False
766+ global_info ["notch_filter " ] = False
762767
763768 if not file_format == "header-attached" :
764769 # filter out dtypes without any values
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