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[AArch64] Add assembly/disassembly for zeroing SVE FCVT{X} and BFCVT (llvm#113916)
This patch adds assembly/disassembly support for the following SVE2.2 instructions - FCVT (zeroing) - FCVTX (zeroing) - BFCVT (zeroing) In accordance with: https://developer.arm.com/documentation/ddi0602/2024-09/SVE-Instructions
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‎llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td‎

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4225,15 +4225,22 @@ defm TBLQ_ZZZ : sve2p1_tblq<"tblq", int_aarch64_sve_tblq>;
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// SME2.2 or SVE2.2 instructions
42264226
//===----------------------------------------------------------------------===//
42274227
let Predicates = [HasSVE2p2orSME2p2] in {
4228+
// SVE Floating-point convert precision, zeroing predicate
4229+
defm FCVT_ZPzZ : sve_fp_z2op_p_zd_b_0<"fcvt">;
4230+
42284231
// SVE2p2 floating-point convert precision down (placing odd), zeroing predicate
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defm FCVTNT_ZPzZ : sve_fp_fcvtntz<"fcvtnt">;
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def FCVTXNT_ZPzZ_DtoS : sve_fp_fcvt2z<0b0010, "fcvtxnt", ZPR32, ZPR64>;
4234+
// Placing even
4235+
def FCVTX_ZPzZ_DtoS : sve_fp_z2op_p_zd<0b0001010, "fcvtx", ZPR64, ZPR32>;
42314236

42324237
// SVE2p2 floating-point convert precision up, zeroing predicate
42334238
defm FCVTLT_ZPzZ : sve_fp_fcvtltz<"fcvtlt">;
42344239

42354240
// SVE2p2 floating-point convert single-to-bf (placing odd), zeroing predicate
42364241
def BFCVTNT_ZPzZ : sve_fp_fcvt2z<0b1010, "bfcvtnt", ZPR16, ZPR32>;
4242+
// Placing corresponding
4243+
def BFCVT_ZPzZ_StoH : sve_fp_z2op_p_zd<0b1001010, "bfcvt", ZPR32, ZPR16>;
42374244

42384245
// Floating-point convert to integer, zeroing predicate
42394246
defm FCVTZS_ZPzZ : sve_fp_z2op_p_zd_d<0b0, "fcvtzs">;

‎llvm/lib/Target/AArch64/SVEInstrFormats.td‎

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Original file line numberDiff line numberDiff line change
@@ -3207,6 +3207,15 @@ multiclass sve_fp_z2op_p_zd_d_flogb<string asm> {
32073207
def _D : sve_fp_z2op_p_zd<0b0011011, asm, ZPR64, ZPR64>;
32083208
}
32093209

3210+
multiclass sve_fp_z2op_p_zd_b_0<string asm> {
3211+
def _StoH : sve_fp_z2op_p_zd<0b1001000, asm, ZPR32, ZPR16>;
3212+
def _HtoS : sve_fp_z2op_p_zd<0b1001001, asm, ZPR16, ZPR32>;
3213+
def _DtoH : sve_fp_z2op_p_zd<0b1101000, asm, ZPR64, ZPR16>;
3214+
def _HtoD : sve_fp_z2op_p_zd<0b1101001, asm, ZPR16, ZPR64>;
3215+
def _DtoS : sve_fp_z2op_p_zd<0b1101010, asm, ZPR64, ZPR32>;
3216+
def _StoD : sve_fp_z2op_p_zd<0b1101011, asm, ZPR32, ZPR64>;
3217+
}
3218+
32103219
//===----------------------------------------------------------------------===//
32113220
// SVE Integer Arithmetic - Binary Predicated Group
32123221
//===----------------------------------------------------------------------===//

‎llvm/test/MC/AArch64/SVE/bfcvt-diagnostics.s‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,7 @@ bfcvt z0.h, p0/m, z1.h
1111
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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1313
bfcvt z0.h, p0/z, z1.s
14-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
14+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction requires: sme2p2 or sve2p2
1515
// CHECK-NEXT: bfcvt z0.h, p0/z, z1.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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‎llvm/test/MC/AArch64/SVE2/fcvtx-diagnostics.s‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -29,7 +29,7 @@ fcvtx z0.d, p0/m, z0.d
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// Invalid predicate operation
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3131
fcvtx z0.s, p0/z, z0.d
32-
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
32+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction requires: sme2p2 or sve2p2
3333
// CHECK-NEXT: fcvtx z0.s, p0/z, z0.d
3434
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
3535

‎llvm/test/MC/AArch64/SVE2p2/bfcvt_z-diagnostics.s‎

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@@ -0,0 +1,60 @@
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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 2>&1 < %s| FileCheck %s
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// --------------------------------------------------------------------------//
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// Invalid operand
5+
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bfcvt z0.b, p0/z, z0.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
8+
// CHECK-NEXT: bfcvt z0.b, p0/z, z0.b
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
10+
11+
// --------------------------------------------------------------------------//
12+
// Invalid element width
13+
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bfcvt z0.h, p0/z, z0.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: bfcvt z0.h, p0/z, z0.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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bfcvt z0.h, p0/z, z0.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: bfcvt z0.h, p0/z, z0.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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bfcvt z0.s, p0/z, z0.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: bfcvt z0.s, p0/z, z0.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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bfcvt z0.s, p0/z, z0.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: bfcvt z0.s, p0/z, z0.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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bfcvt z0.d, p0/z, z0.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: bfcvt z0.d, p0/z, z0.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Predicate not in restricted predicate range
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bfcvt z0.h, p8/z, z0.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
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// CHECK-NEXT: bfcvt z0.h, p8/z, z0.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Negative tests for instructions that are incompatible with movprfx
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movprfx z0.s, p0/m, z7.s
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bfcvt z0.h, p7/z, z1.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: bfcvt z0.h, p7/z, z1.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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movprfx z0, z7
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bfcvt z0.h, p7/z, z1.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
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// CHECK-NEXT: bfcvt z0.h, p7/z, z1.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

‎llvm/test/MC/AArch64/SVE2p2/bfcvt_z.s‎

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@@ -0,0 +1,33 @@
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
5+
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
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// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \
8+
// RUN: | llvm-objdump -d --mattr=+sve2p2 - | FileCheck %s --check-prefix=CHECK-INST
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \
10+
// RUN: | llvm-objdump -d --mattr=-sve2p2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
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// Disassemble encoding and check the re-encoding (-show-encoding) matches.
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \
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// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
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// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p2 -disassemble -show-encoding \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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bfcvt z0.h, p0/z, z0.s // 01100100-10011010-11000000-00000000
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// CHECK-INST: bfcvt z0.h, p0/z, z0.s
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// CHECK-ENCODING: [0x00,0xc0,0x9a,0x64]
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// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
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// CHECK-UNKNOWN: 649ac000 <unknown>
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bfcvt z21.h, p5/z, z10.s // 01100100-10011010-11010101-01010101
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// CHECK-INST: bfcvt z21.h, p5/z, z10.s
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// CHECK-ENCODING: [0x55,0xd5,0x9a,0x64]
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// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
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// CHECK-UNKNOWN: 649ad555 <unknown>
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bfcvt z31.h, p7/z, z31.s // 01100100-10011010-11011111-11111111
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// CHECK-INST: bfcvt z31.h, p7/z, z31.s
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// CHECK-ENCODING: [0xff,0xdf,0x9a,0x64]
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// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
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// CHECK-UNKNOWN: 649adfff <unknown>

‎llvm/test/MC/AArch64/SVE2p2/fcvt_z-diagnostics.s‎

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@@ -0,0 +1,50 @@
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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 2>&1 < %s| FileCheck %s
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3+
// --------------------------------------------------------------------------//
4+
// Invalid operand
5+
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fcvt z0.b, p0/z, z0.h
7+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: fcvt z0.b, p0/z, z0.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
10+
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// --------------------------------------------------------------------------//
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// Invalid element width
13+
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fcvt z0.h, p0/z, z0.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: fcvt z0.h, p0/z, z0.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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fcvt z0.s, p0/z, z0.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: fcvt z0.s, p0/z, z0.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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fcvt z0.d, p0/z, z0.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: fcvt z0.d, p0/z, z0.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
28+
29+
// --------------------------------------------------------------------------//
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// Predicate not in restricted predicate range
31+
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fcvt z0.s, p8/z, z0.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
34+
// CHECK-NEXT: fcvt z0.s, p8/z, z0.d
35+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
36+
37+
// --------------------------------------------------------------------------//
38+
// Negative tests for instructions that are incompatible with movprfx
39+
40+
movprfx z0.s, p0/m, z7.s
41+
fcvt z0.s, p7/z, z1.d
42+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
43+
// CHECK-NEXT: fcvt z0.s, p7/z, z1.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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46+
movprfx z0, z7
47+
fcvt z0.s, p7/z, z1.d
48+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
49+
// CHECK-NEXT: fcvt z0.s, p7/z, z1.d
50+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

‎llvm/test/MC/AArch64/SVE2p2/fcvt_z.s‎

Lines changed: 57 additions & 0 deletions
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@@ -0,0 +1,57 @@
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \
2+
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3+
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \
4+
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
5+
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
6+
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
7+
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \
8+
// RUN: | llvm-objdump -d --mattr=+sve2p2 - | FileCheck %s --check-prefix=CHECK-INST
9+
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \
10+
// RUN: | llvm-objdump -d --mattr=-sve2p2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
11+
// Disassemble encoding and check the re-encoding (-show-encoding) matches.
12+
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \
13+
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
14+
// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p2 -disassemble -show-encoding \
15+
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
16+
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// convert to half
18+
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fcvt z0.h, p0/z, z0.s // 01100100-10011010-10000000-00000000
20+
// CHECK-INST: fcvt z0.h, p0/z, z0.s
21+
// CHECK-ENCODING: [0x00,0x80,0x9a,0x64]
22+
// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
23+
// CHECK-UNKNOWN: 649a8000 <unknown>
24+
25+
fcvt z23.h, p3/z, z13.d // 01100100-11011010-10001101-10110111
26+
// CHECK-INST: fcvt z23.h, p3/z, z13.d
27+
// CHECK-ENCODING: [0xb7,0x8d,0xda,0x64]
28+
// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
29+
// CHECK-UNKNOWN: 64da8db7 <unknown>
30+
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// convert to single
32+
33+
fcvt z0.s, p0/z, z0.h // 01100100-10011010-10100000-00000000
34+
// CHECK-INST: fcvt z0.s, p0/z, z0.h
35+
// CHECK-ENCODING: [0x00,0xa0,0x9a,0x64]
36+
// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
37+
// CHECK-UNKNOWN: 649aa000 <unknown>
38+
39+
fcvt z31.s, p7/z, z31.d // 01100100-11011010-11011111-11111111
40+
// CHECK-INST: fcvt z31.s, p7/z, z31.d
41+
// CHECK-ENCODING: [0xff,0xdf,0xda,0x64]
42+
// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
43+
// CHECK-UNKNOWN: 64dadfff <unknown>
44+
45+
// convert to double
46+
47+
fcvt z21.d, p5/z, z10.h // 01100100-11011010-10110101-01010101
48+
// CHECK-INST: fcvt z21.d, p5/z, z10.h
49+
// CHECK-ENCODING: [0x55,0xb5,0xda,0x64]
50+
// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
51+
// CHECK-UNKNOWN: 64dab555 <unknown>
52+
53+
fcvt z31.d, p7/z, z31.s // 01100100-11011010-11111111-11111111
54+
// CHECK-INST: fcvt z31.d, p7/z, z31.s
55+
// CHECK-ENCODING: [0xff,0xff,0xda,0x64]
56+
// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
57+
// CHECK-UNKNOWN: 64daffff <unknown

‎llvm/test/MC/AArch64/SVE2p2/fcvtx_z-diagnostics.s‎

Lines changed: 57 additions & 0 deletions
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@@ -0,0 +1,57 @@
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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 2>&1 < %s| FileCheck %s
2+
3+
// --------------------------------------------------------------------------//
4+
// Invalid element width
5+
6+
fcvtx z0.b, p0/z, z0.b
7+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
8+
// CHECK-NEXT: fcvtx z0.b, p0/z, z0.b
9+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
10+
11+
fcvtx z0.h, p0/z, z0.h
12+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
13+
// CHECK-NEXT: fcvtx z0.h, p0/z, z0.h
14+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
15+
16+
fcvtx z0.s, p0/z, z0.s
17+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
18+
// CHECK-NEXT: fcvtx z0.s, p0/z, z0.s
19+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
20+
21+
fcvtx z0.d, p0/z, z0.d
22+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
23+
// CHECK-NEXT: fcvtx z0.d, p0/z, z0.d
24+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
25+
26+
fcvtx z0.h, p0/z, z0.s
27+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
28+
// CHECK-NEXT: fcvtx z0.h, p0/z, z0.s
29+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
30+
31+
fcvtx z0.b, p0/z, z0.h
32+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
33+
// CHECK-NEXT: fcvtx z0.b, p0/z, z0.h
34+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
35+
36+
// --------------------------------------------------------------------------//
37+
// Predicate not in restricted predicate range
38+
39+
fcvtx z0.s, p8/z, z0.d
40+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
41+
// CHECK-NEXT: fcvtx z0.s, p8/z, z0.d
42+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
43+
44+
// --------------------------------------------------------------------------//
45+
// Negative tests for instructions that are incompatible with movprfx
46+
47+
movprfx z0.s, p0/m, z7.s
48+
fcvtx z0.s, p7/z, z1.d
49+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
50+
// CHECK-NEXT: fcvtx z0.s, p7/z, z1.d
51+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
52+
53+
movprfx z0, z7
54+
fcvtx z0.s, p7/z, z1.d
55+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov
56+
// CHECK-NEXT: fcvtx z0.s, p7/z, z1.d
57+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

‎llvm/test/MC/AArch64/SVE2p2/fcvtx_z.s‎

Lines changed: 33 additions & 0 deletions
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1+
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \
2+
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3+
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \
4+
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
5+
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
6+
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \
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// RUN: | llvm-objdump -d --mattr=+sve2p2 - | FileCheck %s --check-prefix=CHECK-INST
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \
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// RUN: | llvm-objdump -d --mattr=-sve2p2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
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// Disassemble encoding and check the re-encoding (-show-encoding) matches.
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \
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// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
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// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p2 -disassemble -show-encoding \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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fcvtx z0.s, p0/z, z0.d // 01100100-00011010-11000000-00000000
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// CHECK-INST: fcvtx z0.s, p0/z, z0.d
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// CHECK-ENCODING: [0x00,0xc0,0x1a,0x64]
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// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
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// CHECK-UNKNOWN: 641ac000 <unknown>
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fcvtx z23.s, p3/z, z13.d // 01100100-00011010-11001101-10110111
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// CHECK-INST: fcvtx z23.s, p3/z, z13.d
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// CHECK-ENCODING: [0xb7,0xcd,0x1a,0x64]
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// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
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// CHECK-UNKNOWN: 641acdb7 <unknown>
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fcvtx z31.s, p7/z, z31.d // 01100100-00011010-11011111-11111111
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// CHECK-INST: fcvtx z31.s, p7/z, z31.d
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// CHECK-ENCODING: [0xff,0xdf,0x1a,0x64]
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// CHECK-ERROR: instruction requires: sme2p2 or sve2p2
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// CHECK-UNKNOWN: 641adfff <unknown>

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