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[RISCV] Add tests for deinterleave shuffles w/o vnsrl.vv
With SEW=64, the vnsrl trick we primary rely on does not work. This is handled correctly today, but we have fairly minimal testing of the resulting shuffles which makes it hard to demonstrate value of an upcoming change.
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‎llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll‎

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Original file line numberDiff line numberDiff line change
@@ -90,6 +90,64 @@ define {<2 x i64>, <2 x i64>} @vector_deinterleave_v2i64_v4i64(<4 x i64> %vec) {
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ret {<2 x i64>, <2 x i64>} %retval
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}
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define {<4 x i64>, <4 x i64>} @vector_deinterleave_v4i64_v8i64(<8 x i64> %vec) {
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; CHECK-LABEL: vector_deinterleave_v4i64_v8i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
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; CHECK-NEXT: vid.v v12
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; CHECK-NEXT: vadd.vv v14, v12, v12
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; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
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; CHECK-NEXT: vrgatherei16.vv v12, v8, v14
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; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
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; CHECK-NEXT: vadd.vi v15, v14, -4
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; CHECK-NEXT: vmv.v.i v0, 12
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; CHECK-NEXT: vsetivli zero, 4, e64, m4, ta, ma
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; CHECK-NEXT: vslidedown.vi v16, v8, 4
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; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
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; CHECK-NEXT: vrgatherei16.vv v12, v16, v15, v0.t
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; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
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; CHECK-NEXT: vadd.vi v15, v14, 1
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; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
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; CHECK-NEXT: vrgatherei16.vv v10, v8, v15
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; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
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; CHECK-NEXT: vadd.vi v8, v14, -3
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; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu
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; CHECK-NEXT: vrgatherei16.vv v10, v16, v8, v0.t
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; CHECK-NEXT: vmv.v.v v8, v12
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; CHECK-NEXT: ret
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%retval = call {<4 x i64>, <4 x i64>} @llvm.vector.deinterleave2.v8i64(<8 x i64> %vec)
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ret {<4 x i64>, <4 x i64>} %retval
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}
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define {<8 x i64>, <8 x i64>} @vector_deinterleave_v8i64_v16i64(<16 x i64> %vec) {
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; CHECK-LABEL: vector_deinterleave_v8i64_v16i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmv8r.v v16, v8
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; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
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; CHECK-NEXT: vid.v v8
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; CHECK-NEXT: vadd.vv v7, v8, v8
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; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
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; CHECK-NEXT: vrgatherei16.vv v8, v16, v7
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; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
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; CHECK-NEXT: vmv.v.i v0, -16
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; CHECK-NEXT: vadd.vi v12, v7, -8
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; CHECK-NEXT: vsetivli zero, 8, e64, m8, ta, ma
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; CHECK-NEXT: vslidedown.vi v24, v16, 8
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; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, mu
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; CHECK-NEXT: vrgatherei16.vv v8, v24, v12, v0.t
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; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
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; CHECK-NEXT: vadd.vi v20, v7, 1
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; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
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; CHECK-NEXT: vrgatherei16.vv v12, v16, v20
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; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
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; CHECK-NEXT: vadd.vi v16, v7, -7
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; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu
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; CHECK-NEXT: vrgatherei16.vv v12, v24, v16, v0.t
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; CHECK-NEXT: ret
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%retval = call {<8 x i64>, <8 x i64>} @llvm.vector.deinterleave2.v16i64(<16 x i64> %vec)
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ret {<8 x i64>, <8 x i64>} %retval
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}
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declare {<16 x i1>, <16 x i1>} @llvm.vector.deinterleave2.v32i1(<32 x i1>)
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declare {<16 x i8>, <16 x i8>} @llvm.vector.deinterleave2.v32i8(<32 x i8>)
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declare {<8 x i16>, <8 x i16>} @llvm.vector.deinterleave2.v16i16(<16 x i16>)
@@ -176,9 +234,41 @@ define {<2 x double>, <2 x double>} @vector_deinterleave_v2f64_v4f64(<4 x double
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ret {<2 x double>, <2 x double>} %retval
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}
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define {<4 x double>, <4 x double>} @vector_deinterleave_v4f64_v8f64(<8 x double> %vec) {
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; CHECK-LABEL: vector_deinterleave_v4f64_v8f64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
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; CHECK-NEXT: vid.v v12
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; CHECK-NEXT: vadd.vv v14, v12, v12
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; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
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; CHECK-NEXT: vrgatherei16.vv v12, v8, v14
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; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
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; CHECK-NEXT: vadd.vi v15, v14, -4
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; CHECK-NEXT: vmv.v.i v0, 12
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; CHECK-NEXT: vsetivli zero, 4, e64, m4, ta, ma
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; CHECK-NEXT: vslidedown.vi v16, v8, 4
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; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, mu
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; CHECK-NEXT: vrgatherei16.vv v12, v16, v15, v0.t
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; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
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; CHECK-NEXT: vadd.vi v15, v14, 1
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; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
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; CHECK-NEXT: vrgatherei16.vv v10, v8, v15
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; CHECK-NEXT: vsetvli zero, zero, e16, mf2, ta, ma
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; CHECK-NEXT: vadd.vi v8, v14, -3
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; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu
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; CHECK-NEXT: vrgatherei16.vv v10, v16, v8, v0.t
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; CHECK-NEXT: vmv.v.v v8, v12
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; CHECK-NEXT: ret
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%retval = call {<4 x double>, <4 x double>} @llvm.vector.deinterleave2.v8f64(<8 x double> %vec)
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ret {<4 x double>, <4 x double>} %retval
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}
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declare {<2 x half>,<2 x half>} @llvm.vector.deinterleave2.v4f16(<4 x half>)
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declare {<4 x half>, <4 x half>} @llvm.vector.deinterleave2.v8f16(<8 x half>)
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declare {<2 x float>, <2 x float>} @llvm.vector.deinterleave2.v4f32(<4 x float>)
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declare {<8 x half>, <8 x half>} @llvm.vector.deinterleave2.v16f16(<16 x half>)
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declare {<4 x float>, <4 x float>} @llvm.vector.deinterleave2.v8f32(<8 x float>)
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declare {<2 x double>, <2 x double>} @llvm.vector.deinterleave2.v4f64(<4 x double>)
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;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
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; RV32: {{.*}}
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; RV64: {{.*}}

‎llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll‎

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -84,6 +84,22 @@ define {<vscale x 2 x i64>, <vscale x 2 x i64>} @vector_deinterleave_nxv2i64_nxv
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ret {<vscale x 2 x i64>, <vscale x 2 x i64>} %retval
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}
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define {<vscale x 4 x i64>, <vscale x 4 x i64>} @vector_deinterleave_nxv4i64_nxv8i64(<vscale x 8 x i64> %vec) {
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; CHECK-LABEL: vector_deinterleave_nxv4i64_nxv8i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
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; CHECK-NEXT: vid.v v16
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; CHECK-NEXT: vadd.vv v24, v16, v16
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; CHECK-NEXT: vrgather.vv v16, v8, v24
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; CHECK-NEXT: vadd.vi v24, v24, 1
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; CHECK-NEXT: vrgather.vv v0, v8, v24
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; CHECK-NEXT: vmv4r.v v8, v16
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; CHECK-NEXT: vmv4r.v v12, v0
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; CHECK-NEXT: ret
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%retval = call {<vscale x 4 x i64>, <vscale x 4 x i64>} @llvm.vector.deinterleave2.nxv8i64(<vscale x 8 x i64> %vec)
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ret {<vscale x 4 x i64>, <vscale x 4 x i64>} %retval
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}
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declare {<vscale x 16 x i1>, <vscale x 16 x i1>} @llvm.vector.deinterleave2.nxv32i1(<vscale x 32 x i1>)
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declare {<vscale x 16 x i8>, <vscale x 16 x i8>} @llvm.vector.deinterleave2.nxv32i8(<vscale x 32 x i8>)
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declare {<vscale x 8 x i16>, <vscale x 8 x i16>} @llvm.vector.deinterleave2.nxv16i16(<vscale x 16 x i16>)

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