Skip to content

Commit a989266

Browse files
CarolineConcattoNoumanAmir657
CarolineConcatto
authored and
NoumanAmir657
committed
[LLVM][AArch64]Add assembly/disassembly for compare-and-branch instr… (llvm#113461)
…uctions (llvm#112726) This patch adds the assembly/disassembly for the following instructions: CBB<cc>, CBH<cc>, CB<cc>(immediate), CB<cc>(register) CBBLE, CBBLO, CBBLS, CBBLT CBHLE, CBHLO, CBHLS, CBHLT CBGE, CBHS, CBLE, CBLS (immediate) CBLE, CBLO, CBLS, CBLT(register) According to [1] [1]https://developer.arm.com/documentation/ddi0602 Co-authored-by: Momchil Velikov [email protected] Co-authored-by: Spencer Abson [email protected] This patch was reverted(git commit 83c6e2f) and is being submitted again with the fix for buildbot failure in: https://lab.llvm.org/buildbot/#/builders/25/builds/3493 The fix was to replaced a shift left of a possibly negative value with a multiplication in DecodePCRelLabel9. Because int64_t ImmVal is signed it needed to replace: (ImmVal << 2) with : (ImmVal * 4)
1 parent 209435c commit a989266

16 files changed

+1527
-1
lines changed

‎llvm/lib/Target/AArch64/AArch64InstrFormats.td‎

Lines changed: 135 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -388,6 +388,46 @@ def uimm16 : Operand<i16>, ImmLeaf<i16, [{return Imm >= 0 && Imm < 65536;}]>{
388388
let ParserMatchClass = AsmImmRange<0, 65535>;
389389
}
390390

391+
def uimm6_64b : Operand<i64>, ImmLeaf<i64, [{ return Imm >= 0 && Imm < 64; }]> {
392+
let ParserMatchClass = UImm6Operand;
393+
}
394+
395+
def uimm6_32b : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 64; }]> {
396+
let ParserMatchClass = UImm6Operand;
397+
}
398+
399+
def UImm6Plus1Operand : AsmOperandClass {
400+
let Name = "UImm6P1";
401+
let DiagnosticType = "InvalidImm1_64";
402+
let RenderMethod = "addImmOperands";
403+
let ParserMethod = "tryParseAdjImm0_63<-1>";
404+
let PredicateMethod = "isImmInRange<0,63>";
405+
}
406+
407+
def UImm6Minus1Operand : AsmOperandClass {
408+
let Name = "UImm6M1";
409+
let DiagnosticType = "InvalidImmM1_62";
410+
let RenderMethod = "addImmOperands";
411+
let ParserMethod = "tryParseAdjImm0_63<1>";
412+
let PredicateMethod = "isImmInRange<0,63>";
413+
}
414+
415+
def uimm6p1_32b : Operand<i32> {
416+
let ParserMatchClass = UImm6Plus1Operand;
417+
}
418+
419+
def uimm6p1_64b : Operand<i64> {
420+
let ParserMatchClass = UImm6Plus1Operand;
421+
}
422+
423+
def uimm6m1_32b : Operand<i32> {
424+
let ParserMatchClass = UImm6Minus1Operand;
425+
}
426+
427+
def uimm6m1_64b : Operand<i64> {
428+
let ParserMatchClass = UImm6Minus1Operand;
429+
}
430+
391431
def SImm9Operand : SImmOperand<9>;
392432
def simm9 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= -256 && Imm < 256; }]> {
393433
let ParserMatchClass = SImm9Operand;
@@ -657,6 +697,7 @@ class PCRelLabel<int N> : BranchTarget<N> {
657697
def BranchTarget14Operand : BranchTarget<14>;
658698
def BranchTarget26Operand : BranchTarget<26>;
659699
def PCRelLabel19Operand : PCRelLabel<19>;
700+
def PCRelLabel9Operand : PCRelLabel<9>;
660701

661702
def MovWSymbolG3AsmOperand : AsmOperandClass {
662703
let Name = "MovWSymbolG3";
@@ -2158,6 +2199,17 @@ def am_brcond : Operand<OtherVT> {
21582199
let OperandType = "OPERAND_PCREL";
21592200
}
21602201

2202+
// Conditional branch target. 9-bit immediate. The low two bits of the target
2203+
// offset are implied zero and so are not part of the immediate.
2204+
def am_brcmpcond : Operand<OtherVT> {
2205+
let EncoderMethod = "getCondCompBranchTargetOpValue";
2206+
let DecoderMethod = "DecodePCRelLabel9";
2207+
let PrintMethod = "printAlignedLabel";
2208+
let ParserMatchClass = PCRelLabel9Operand;
2209+
let OperandType = "OPERAND_PCREL";
2210+
}
2211+
2212+
21612213
class BranchCond<bit bit4, string mnemonic>
21622214
: I<(outs), (ins ccode:$cond, am_brcond:$target),
21632215
mnemonic, ".$cond\t$target", "",
@@ -12911,6 +12963,89 @@ class MulAccumCPA<bit isSub, string asm>
1291112963
let Inst{31} = 0b1;
1291212964
}
1291312965

12966+
12967+
//----------------------------------------------------------------------------
12968+
// 2024 Armv9.6 Extensions
12969+
//----------------------------------------------------------------------------
12970+
12971+
//---
12972+
// Compare-and-branch instructions.
12973+
//---
12974+
12975+
class BaseCmpBranchRegister<RegisterClass regtype, bit sf, bits<3> cc,
12976+
bits<2>sz, string asm>
12977+
: I<(outs), (ins regtype:$Rt, regtype:$Rm, am_brcmpcond:$target),
12978+
asm, "\t$Rt, $Rm, $target", "",
12979+
[]>,
12980+
Sched<[WriteBr]> {
12981+
let isBranch = 1;
12982+
let isTerminator = 1;
12983+
12984+
bits<5> Rm;
12985+
bits<5> Rt;
12986+
bits<9> target;
12987+
let Inst{31} = sf;
12988+
let Inst{30-24} = 0b1110100;
12989+
let Inst{23-21} = cc;
12990+
let Inst{20-16} = Rm;
12991+
let Inst{15-14} = sz;
12992+
let Inst{13-5} = target;
12993+
let Inst{4-0} = Rt;
12994+
}
12995+
12996+
multiclass CmpBranchRegister<bits<3> cc, string asm> {
12997+
def Wrr : BaseCmpBranchRegister<GPR32, 0b0, cc, 0b00, asm>;
12998+
def Xrr : BaseCmpBranchRegister<GPR64, 0b1, cc, 0b00, asm>;
12999+
}
13000+
13001+
class BaseCmpBranchImmediate<RegisterClass regtype, bit sf, bits<3> cc,
13002+
Operand imm_ty, string asm>
13003+
: I<(outs), (ins regtype:$Rt, imm_ty:$imm, am_brcmpcond:$target),
13004+
asm, "\t$Rt, $imm, $target", "",
13005+
[]>,
13006+
Sched<[WriteBr]> {
13007+
let isBranch = 1;
13008+
let isTerminator = 1;
13009+
13010+
bits<5> Rt;
13011+
bits<6> imm;
13012+
bits<9> target;
13013+
let Inst{31} = sf;
13014+
let Inst{30-24} = 0b1110101;
13015+
let Inst{23-21} = cc;
13016+
let Inst{20-15} = imm;
13017+
let Inst{14} = 0b0;
13018+
let Inst{13-5} = target;
13019+
let Inst{4-0} = Rt;
13020+
}
13021+
13022+
multiclass CmpBranchImmediate<bits<3> cc, string imm_ty, string asm> {
13023+
def Wri : BaseCmpBranchImmediate<GPR32, 0b0, cc, !cast<Operand>(imm_ty # "_32b"), asm>;
13024+
def Xri : BaseCmpBranchImmediate<GPR64, 0b1, cc, !cast<Operand>(imm_ty # "_64b"), asm>;
13025+
}
13026+
13027+
multiclass CmpBranchImmediateAlias<string mnemonic, string insn, string imm_ty> {
13028+
def : InstAlias<mnemonic # "\t$Rt, $imm, $target",
13029+
(!cast<Instruction>(insn # "Wri") GPR32:$Rt,
13030+
!cast<Operand>(imm_ty # "_32b"):$imm,
13031+
am_brcmpcond:$target), 0>;
13032+
def : InstAlias<mnemonic # "\t$Rt, $imm, $target",
13033+
(!cast<Instruction>(insn # "Xri") GPR64:$Rt,
13034+
!cast<Operand>(imm_ty # "_64b"):$imm,
13035+
am_brcmpcond:$target), 0>;
13036+
}
13037+
13038+
multiclass CmpBranchWRegisterAlias<string mnemonic, string insn> {
13039+
def : InstAlias<mnemonic # "\t$Rt, $Rm, $target",
13040+
(!cast<Instruction>(insn # "Wrr") GPR32:$Rm, GPR32:$Rt, am_brcmpcond:$target), 0>;
13041+
}
13042+
13043+
multiclass CmpBranchRegisterAlias<string mnemonic, string insn> {
13044+
defm : CmpBranchWRegisterAlias<mnemonic, insn>;
13045+
13046+
def : InstAlias<mnemonic # "\t$Rt, $Rm, $target",
13047+
(!cast<Instruction>(insn # "Xrr") GPR64:$Rm, GPR64:$Rt, am_brcmpcond:$target), 0>;
13048+
}
1291413049
//----------------------------------------------------------------------------
1291513050
// Allow the size specifier tokens to be upper case, not just lower.
1291613051
def : TokenAlias<".4B", ".4b">; // Add dot product

‎llvm/lib/Target/AArch64/AArch64InstrInfo.td‎

Lines changed: 51 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -10423,6 +10423,57 @@ defm : PromoteBinaryv8f16Tov4f32<any_fdiv, FDIVv4f32>;
1042310423
defm : PromoteBinaryv8f16Tov4f32<any_fmul, FMULv4f32>;
1042410424
defm : PromoteBinaryv8f16Tov4f32<any_fsub, FSUBv4f32>;
1042510425

10426+
let Predicates = [HasCMPBR] in {
10427+
defm CBGT : CmpBranchRegister<0b000, "cbgt">;
10428+
defm CBGE : CmpBranchRegister<0b001, "cbge">;
10429+
defm CBHI : CmpBranchRegister<0b010, "cbhi">;
10430+
defm CBHS : CmpBranchRegister<0b011, "cbhs">;
10431+
defm CBEQ : CmpBranchRegister<0b110, "cbeq">;
10432+
defm CBNE : CmpBranchRegister<0b111, "cbne">;
10433+
10434+
def CBHGTWrr : BaseCmpBranchRegister<GPR32, 0b0, 0b000, 0b11, "cbhgt">;
10435+
def CBHGEWrr : BaseCmpBranchRegister<GPR32, 0b0, 0b001, 0b11, "cbhge">;
10436+
def CBHHIWrr : BaseCmpBranchRegister<GPR32, 0b0, 0b010, 0b11, "cbhhi">;
10437+
def CBHHSWrr : BaseCmpBranchRegister<GPR32, 0b0, 0b011, 0b11, "cbhhs">;
10438+
def CBHEQWrr : BaseCmpBranchRegister<GPR32, 0b0, 0b110, 0b11, "cbheq">;
10439+
def CBHNEWrr : BaseCmpBranchRegister<GPR32, 0b0, 0b111, 0b11, "cbhne">;
10440+
10441+
def CBBGTWrr : BaseCmpBranchRegister<GPR32, 0b0, 0b000, 0b10, "cbbgt">;
10442+
def CBBGEWrr : BaseCmpBranchRegister<GPR32, 0b0, 0b001, 0b10, "cbbge">;
10443+
def CBBHIWrr : BaseCmpBranchRegister<GPR32, 0b0, 0b010, 0b10, "cbbhi">;
10444+
def CBBHSWrr : BaseCmpBranchRegister<GPR32, 0b0, 0b011, 0b10, "cbbhs">;
10445+
def CBBEQWrr : BaseCmpBranchRegister<GPR32, 0b0, 0b110, 0b10, "cbbeq">;
10446+
def CBBNEWrr : BaseCmpBranchRegister<GPR32, 0b0, 0b111, 0b10, "cbbne">;
10447+
10448+
defm CBGT : CmpBranchImmediate<0b000, "uimm6", "cbgt">;
10449+
defm CBLT : CmpBranchImmediate<0b001, "uimm6", "cblt">;
10450+
defm CBHI : CmpBranchImmediate<0b010, "uimm6", "cbhi">;
10451+
defm CBLO : CmpBranchImmediate<0b011, "uimm6", "cblo">;
10452+
defm CBEQ : CmpBranchImmediate<0b110, "uimm6", "cbeq">;
10453+
defm CBNE : CmpBranchImmediate<0b111, "uimm6", "cbne">;
10454+
10455+
defm : CmpBranchImmediateAlias<"cbge", "CBGT", "uimm6p1">;
10456+
defm : CmpBranchImmediateAlias<"cbhs", "CBHI", "uimm6p1">;
10457+
defm : CmpBranchImmediateAlias<"cble", "CBLT", "uimm6m1">;
10458+
defm : CmpBranchImmediateAlias<"cbls", "CBLO", "uimm6m1">;
10459+
10460+
defm : CmpBranchRegisterAlias<"cble", "CBGE">;
10461+
defm : CmpBranchRegisterAlias<"cblo", "CBHI">;
10462+
defm : CmpBranchRegisterAlias<"cbls", "CBHS">;
10463+
defm : CmpBranchRegisterAlias<"cblt", "CBGT">;
10464+
10465+
defm : CmpBranchWRegisterAlias<"cbble", "CBBGE">;
10466+
defm : CmpBranchWRegisterAlias<"cbblo", "CBBHI">;
10467+
defm : CmpBranchWRegisterAlias<"cbbls", "CBBHS">;
10468+
defm : CmpBranchWRegisterAlias<"cbblt", "CBBGT">;
10469+
10470+
defm : CmpBranchWRegisterAlias<"cbhle", "CBHGE">;
10471+
defm : CmpBranchWRegisterAlias<"cbhlo", "CBHHI">;
10472+
defm : CmpBranchWRegisterAlias<"cbhls", "CBHHS">;
10473+
defm : CmpBranchWRegisterAlias<"cbhlt", "CBHGT">;
10474+
} // HasCMPBR
10475+
10476+
1042610477
//===-----------------------------------------------------===//
1042710478
// Atomic floating-point in-memory instructions (FEAT_LSFE)
1042810479
//===-----------------------------------------------------===//

‎llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp‎

Lines changed: 51 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2093,6 +2093,20 @@ class AArch64Operand : public MCParsedAsmOperand {
20932093
Inst.addOperand(MCOperand::createImm(MCE->getValue() >> 2));
20942094
}
20952095

2096+
void addPCRelLabel9Operands(MCInst &Inst, unsigned N) const {
2097+
// Branch operands don't encode the low bits, so shift them off
2098+
// here. If it's a label, however, just put it on directly as there's
2099+
// not enough information now to do anything.
2100+
assert(N == 1 && "Invalid number of operands!");
2101+
const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
2102+
if (!MCE) {
2103+
addExpr(Inst, getImm());
2104+
return;
2105+
}
2106+
assert(MCE && "Invalid constant immediate operand!");
2107+
Inst.addOperand(MCOperand::createImm(MCE->getValue() >> 2));
2108+
}
2109+
20962110
void addBranchTarget14Operands(MCInst &Inst, unsigned N) const {
20972111
// Branch operands don't encode the low bits, so shift them off
20982112
// here. If it's a label, however, just put it on directly as there's
@@ -5988,6 +6002,8 @@ bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode,
59886002
return Error(Loc, "immediate must be an integer in range [1, 32].");
59896003
case Match_InvalidImm1_64:
59906004
return Error(Loc, "immediate must be an integer in range [1, 64].");
6005+
case Match_InvalidImmM1_62:
6006+
return Error(Loc, "immediate must be an integer in range [-1, 62].");
59916007
case Match_InvalidMemoryIndexedRange2UImm0:
59926008
return Error(Loc, "vector select offset must be the immediate range 0:1.");
59936009
case Match_InvalidMemoryIndexedRange2UImm1:
@@ -6761,6 +6777,7 @@ bool AArch64AsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
67616777
case Match_InvalidImm1_16:
67626778
case Match_InvalidImm1_32:
67636779
case Match_InvalidImm1_64:
6780+
case Match_InvalidImmM1_62:
67646781
case Match_InvalidMemoryIndexedRange2UImm0:
67656782
case Match_InvalidMemoryIndexedRange2UImm1:
67666783
case Match_InvalidMemoryIndexedRange2UImm2:
@@ -8229,3 +8246,37 @@ ParseStatus AArch64AsmParser::tryParseImmRange(OperandVector &Operands) {
82298246
AArch64Operand::CreateImmRange(ImmFVal, ImmLVal, S, E, getContext()));
82308247
return ParseStatus::Success;
82318248
}
8249+
8250+
template <int Adj>
8251+
ParseStatus AArch64AsmParser::tryParseAdjImm0_63(OperandVector &Operands) {
8252+
SMLoc S = getLoc();
8253+
8254+
parseOptionalToken(AsmToken::Hash);
8255+
bool IsNegative = parseOptionalToken(AsmToken::Minus);
8256+
8257+
if (getTok().isNot(AsmToken::Integer))
8258+
return ParseStatus::NoMatch;
8259+
8260+
const MCExpr *Ex;
8261+
if (getParser().parseExpression(Ex))
8262+
return ParseStatus::NoMatch;
8263+
8264+
int64_t Imm = dyn_cast<MCConstantExpr>(Ex)->getValue();
8265+
if (IsNegative)
8266+
Imm = -Imm;
8267+
8268+
// We want an adjusted immediate in the range [0, 63]. If we don't have one,
8269+
// return a value, which is certain to trigger a error message about invalid
8270+
// immediate range instead of a non-descriptive invalid operand error.
8271+
static_assert(Adj == 1 || Adj == -1, "Unsafe immediate adjustment");
8272+
if (Imm == INT64_MIN || Imm == INT64_MAX || Imm + Adj < 0 || Imm + Adj > 63)
8273+
Imm = -2;
8274+
else
8275+
Imm += Adj;
8276+
8277+
SMLoc E = SMLoc::getFromPointer(getLoc().getPointer() - 1);
8278+
Operands.push_back(AArch64Operand::CreateImm(
8279+
MCConstantExpr::create(Imm, getContext()), S, E, getContext()));
8280+
8281+
return ParseStatus::Success;
8282+
}

‎llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp‎

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -82,6 +82,9 @@ static DecodeStatus DecodePCRelLabel16(MCInst &Inst, unsigned Imm,
8282
static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm,
8383
uint64_t Address,
8484
const MCDisassembler *Decoder);
85+
static DecodeStatus DecodePCRelLabel9(MCInst &Inst, unsigned Imm,
86+
uint64_t Address,
87+
const MCDisassembler *Decoder);
8588
static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm,
8689
uint64_t Address,
8790
const MCDisassembler *Decoder);
@@ -501,6 +504,20 @@ static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm,
501504
return Success;
502505
}
503506

507+
static DecodeStatus DecodePCRelLabel9(MCInst &Inst, unsigned Imm, uint64_t Addr,
508+
const MCDisassembler *Decoder) {
509+
int64_t ImmVal = Imm;
510+
511+
// Sign-extend 9-bit immediate.
512+
if (ImmVal & (1 << (9 - 1)))
513+
ImmVal |= ~((1LL << 9) - 1);
514+
515+
if (!Decoder->tryAddingSymbolicOperand(Inst, (ImmVal * 4), Addr,
516+
/*IsBranch=*/true, 0, 0, 4))
517+
Inst.addOperand(MCOperand::createImm(ImmVal));
518+
return Success;
519+
}
520+
504521
static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm,
505522
uint64_t Address,
506523
const MCDisassembler *Decoder) {

‎llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp‎

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -66,6 +66,7 @@ class AArch64AsmBackend : public MCAsmBackend {
6666
{"fixup_aarch64_ldst_imm12_scale16", 10, 12, 0},
6767
{"fixup_aarch64_ldr_pcrel_imm19", 5, 19, PCRelFlagVal},
6868
{"fixup_aarch64_movw", 5, 16, 0},
69+
{"fixup_aarch64_pcrel_branch9", 5, 9, PCRelFlagVal},
6970
{"fixup_aarch64_pcrel_branch14", 5, 14, PCRelFlagVal},
7071
{"fixup_aarch64_pcrel_branch16", 5, 16, PCRelFlagVal},
7172
{"fixup_aarch64_pcrel_branch19", 5, 19, PCRelFlagVal},
@@ -120,6 +121,7 @@ static unsigned getFixupKindNumBytes(unsigned Kind) {
120121
return 2;
121122

122123
case AArch64::fixup_aarch64_movw:
124+
case AArch64::fixup_aarch64_pcrel_branch9:
123125
case AArch64::fixup_aarch64_pcrel_branch14:
124126
case AArch64::fixup_aarch64_pcrel_branch16:
125127
case AArch64::fixup_aarch64_add_imm12:
@@ -307,6 +309,14 @@ static uint64_t adjustFixupValue(const MCFixup &Fixup, const MCValue &Target,
307309
}
308310
return Value;
309311
}
312+
case AArch64::fixup_aarch64_pcrel_branch9:
313+
// Signed 11-bit(9bits + 2 shifts) label
314+
if (!isInt<11>(SignedValue))
315+
Ctx.reportError(Fixup.getLoc(), "fixup value out of range");
316+
// Low two bits are not encoded (4-byte alignment assumed).
317+
if (Value & 0b11)
318+
Ctx.reportError(Fixup.getLoc(), "fixup not sufficiently aligned");
319+
return (Value >> 2) & 0x1ff;
310320
case AArch64::fixup_aarch64_pcrel_branch14:
311321
// Signed 16-bit immediate
312322
if (!isInt<16>(SignedValue))
@@ -391,6 +401,7 @@ unsigned AArch64AsmBackend::getFixupKindContainereSizeInBytes(unsigned Kind) con
391401
return 8;
392402

393403
case AArch64::fixup_aarch64_movw:
404+
case AArch64::fixup_aarch64_pcrel_branch9:
394405
case AArch64::fixup_aarch64_pcrel_branch14:
395406
case AArch64::fixup_aarch64_pcrel_branch16:
396407
case AArch64::fixup_aarch64_add_imm12:

‎llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -188,6 +188,11 @@ unsigned AArch64ELFObjectWriter::getRelocType(MCContext &Ctx,
188188
Ctx.reportError(Fixup.getLoc(),
189189
"relocation of PAC/AUT instructions is not supported");
190190
return ELF::R_AARCH64_NONE;
191+
case AArch64::fixup_aarch64_pcrel_branch9:
192+
Ctx.reportError(
193+
Fixup.getLoc(),
194+
"relocation of compare-and-branch instructions not supported");
195+
return ELF::R_AARCH64_NONE;
191196
case AArch64::fixup_aarch64_pcrel_branch19:
192197
return R_CLS(CONDBR19);
193198
default:

‎llvm/lib/Target/AArch64/MCTargetDesc/AArch64FixupKinds.h‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -40,6 +40,9 @@ enum Fixups {
4040
// FIXME: comment
4141
fixup_aarch64_movw,
4242

43+
// The high 9 bits of a 11-bit pc-relative immediate.
44+
fixup_aarch64_pcrel_branch9,
45+
4346
// The high 14 bits of a 21-bit pc-relative immediate.
4447
fixup_aarch64_pcrel_branch14,
4548

0 commit comments

Comments
 (0)