NMSIS/Core: Use 1UL for logical left shift

fanghuaqi · fanghuaqi · commit f2d5cc6032ad · 2025-05-21T13:11:30.000+08:00
Signed-off-by: Huaqi Fang &lt;578567190@qq.com&gt;
diff --git a/NMSIS/Core/Include/core_feature_base.h b/NMSIS/Core/Include/core_feature_base.h
@@ -881,7 +881,7 @@ __STATIC_FORCEINLINE void __disable_sw_irq(void)
  */
 __STATIC_FORCEINLINE void __disable_core_irq(uint32_t irq)
 {
-    __RV_CSR_CLEAR(CSR_MIE, 1 << irq);
+    __RV_CSR_CLEAR(CSR_MIE, 1UL << irq);
 }
 
 /**
@@ -892,7 +892,7 @@ __STATIC_FORCEINLINE void __disable_core_irq(uint32_t irq)
  */
 __STATIC_FORCEINLINE void __enable_core_irq(uint32_t irq)
 {
-    __RV_CSR_SET(CSR_MIE, 1 << irq);
+    __RV_CSR_SET(CSR_MIE, 1UL << irq);
 }
 
 /**
@@ -914,7 +914,7 @@ __STATIC_FORCEINLINE uint32_t __get_core_irq_pending(uint32_t irq)
  */
 __STATIC_FORCEINLINE void __clear_core_irq_pending(uint32_t irq)
 {
-    __RV_CSR_CLEAR(CSR_MIP, 1 << irq);
+    __RV_CSR_CLEAR(CSR_MIP, 1UL << irq);
 }
 
 /**
@@ -1013,7 +1013,7 @@ __STATIC_FORCEINLINE void __disable_sw_irq_s(void)
  */
 __STATIC_FORCEINLINE void __disable_core_irq_s(uint32_t irq)
 {
-    __RV_CSR_CLEAR(CSR_SIE, 1 << irq);
+    __RV_CSR_CLEAR(CSR_SIE, 1UL << irq);
 }
 
 /**
@@ -1024,7 +1024,7 @@ __STATIC_FORCEINLINE void __disable_core_irq_s(uint32_t irq)
  */
 __STATIC_FORCEINLINE void __enable_core_irq_s(uint32_t irq)
 {
-    __RV_CSR_SET(CSR_SIE, 1 << irq);
+    __RV_CSR_SET(CSR_SIE, 1UL << irq);
 }
 
 /**
@@ -1046,7 +1046,7 @@ __STATIC_FORCEINLINE uint32_t __get_core_irq_pending_s(uint32_t irq)
  */
 __STATIC_FORCEINLINE void __clear_core_irq_pending_s(uint32_t irq)
 {
-    __RV_CSR_CLEAR(CSR_SIP, 1 << irq);
+    __RV_CSR_CLEAR(CSR_SIP, 1UL << irq);
 }
 
 /**
@@ -1463,7 +1463,7 @@ __STATIC_FORCEINLINE void __disable_minstret_counter(void)
  */
 __STATIC_FORCEINLINE void __enable_mhpm_counter(unsigned long idx)
 {
-    __RV_CSR_CLEAR(CSR_MCOUNTINHIBIT, (1 << idx));
+    __RV_CSR_CLEAR(CSR_MCOUNTINHIBIT, (1UL << idx));
 }
 
 /**
@@ -1474,7 +1474,7 @@ __STATIC_FORCEINLINE void __enable_mhpm_counter(unsigned long idx)
  */
 __STATIC_FORCEINLINE void __disable_mhpm_counter(unsigned long idx)
 {
-    __RV_CSR_SET(CSR_MCOUNTINHIBIT, (1 << idx));
+    __RV_CSR_SET(CSR_MCOUNTINHIBIT, (1UL << idx));
 }
 
 /**
diff --git a/NMSIS/Core/Include/core_feature_cache.h b/NMSIS/Core/Include/core_feature_cache.h
@@ -261,12 +261,12 @@ __STATIC_FORCEINLINE int32_t GetICacheInfo(CacheInfo_Type *info)
     }
     CSR_MICFGINFO_Type csr_ccfg;
     csr_ccfg.d = __RV_CSR_READ(CSR_MICFG_INFO);
-    info->setperway = (1 << csr_ccfg.b.set) << 3;
+    info->setperway = (1UL << csr_ccfg.b.set) << 3;
     info->ways = (1 + csr_ccfg.b.way);
     if (csr_ccfg.b.lsize == 0) {
         info->linesize = 0;
     } else {
-        info->linesize = (1 << (csr_ccfg.b.lsize - 1)) << 3;
+        info->linesize = (1UL << (csr_ccfg.b.lsize - 1)) << 3;
     }
     info->size = info->setperway * info->ways * info->linesize;
     return 0;
@@ -825,12 +825,12 @@ __STATIC_FORCEINLINE int32_t GetDCacheInfo(CacheInfo_Type *info)
     }
     CSR_MDCFGINFO_Type csr_ccfg;
     csr_ccfg.d = __RV_CSR_READ(CSR_MDCFG_INFO);
-    info->setperway = (1 << csr_ccfg.b.set) << 3;
+    info->setperway = (1UL << csr_ccfg.b.set) << 3;
     info->ways = (1 + csr_ccfg.b.way);
     if (csr_ccfg.b.lsize == 0) {
         info->linesize = 0;
     } else {
-        info->linesize = (1 << (csr_ccfg.b.lsize - 1)) << 3;
+        info->linesize = (1UL << (csr_ccfg.b.lsize - 1)) << 3;
     }
     info->size = info->setperway * info->ways * info->linesize;
     return 0;
diff --git a/NMSIS/Core/Include/core_feature_cidu.h b/NMSIS/Core/Include/core_feature_cidu.h
@@ -62,7 +62,7 @@ extern "C" {
 #endif
 
 #define CIDU_BASE                                __CIDU_BASEADDR
-#define CIDU_RECEIVE_INTERRUPT_EN(core_id)       (0x1U << core_id)   /*!< Indicates the core can receive corresponding interrupt */
+#define CIDU_RECEIVE_INTERRUPT_EN(core_id)       (0x1UL << core_id)   /*!< Indicates the core can receive corresponding interrupt */
 
 #define CIDU_CORE_INT_STATUS_OFS      0x0        /*!< Core n Inter Core Interrupt status register base offset */
 #define CIDU_SEMAPHORE_OFS            0x80       /*!< Semaphore n register base offset */
@@ -187,7 +187,7 @@ __STATIC_FORCEINLINE long CIDU_SetFirstClaimMode(uint32_t int_id, uint32_t core_
 {
     uint32_t val = 0;
     uint32_t* addr = (uint32_t*)CIDU_INT_MASK_ADDR(int_id);
-    uint32_t mask = 1 << core_id;
+    uint32_t mask = 1UL << core_id;
 
     __SW(addr, mask);
     val = __LW(addr);
@@ -311,7 +311,7 @@ __STATIC_FORCEINLINE void CIDU_ClearInterCoreIntReq(uint32_t send_core_id, uint3
     uint32_t val = 0;
     uint32_t* addr = (uint32_t*)CIDU_CORE_INT_STATUS_ADDR(recv_core_id);
 
-    val = (uint32_t)(1 << send_core_id);
+    val = (uint32_t)(1UL << send_core_id);
     __SW(addr, val);
 }
 /** @} */ /* End of Doxygen Group NMSIS_Core_ICI */
diff --git a/NMSIS/Core/Include/core_feature_eclic.h b/NMSIS/Core/Include/core_feature_eclic.h
@@ -652,7 +652,7 @@ __STATIC_FORCEINLINE void __ECLIC_SetLevelIRQ(IRQn_Type IRQn, uint8_t lvl_abs)
     if (nlbits > intctlbits) {
         nlbits = intctlbits;
     }
-    uint8_t maxlvl = ((1 << nlbits) - 1);
+    uint8_t maxlvl = ((1UL << nlbits) - 1);
     if (lvl_abs > maxlvl) {
         lvl_abs = maxlvl;
     }
@@ -710,7 +710,7 @@ __STATIC_FORCEINLINE void __ECLIC_SetPriorityIRQ(IRQn_Type IRQn, uint8_t pri)
     uint8_t nlbits = __ECLIC_GetCfgNlbits();
     uint8_t intctlbits = (uint8_t)__ECLIC_INTCTLBITS;
     if (nlbits < intctlbits) {
-        uint8_t maxpri = ((1 << (intctlbits - nlbits)) - 1);
+        uint8_t maxpri = ((1UL << (intctlbits - nlbits)) - 1);
         if (pri > maxpri) {
             pri = maxpri;
         }
@@ -1009,7 +1009,7 @@ __STATIC_FORCEINLINE void __ECLIC_SetLevelIRQ_S(IRQn_Type IRQn, uint8_t lvl_abs)
     if (nlbits > intctlbits) {
         nlbits = intctlbits;
     }
-    uint8_t maxlvl = ((1 << nlbits) - 1);
+    uint8_t maxlvl = ((1UL << nlbits) - 1);
     if (lvl_abs > maxlvl) {
         lvl_abs = maxlvl;
     }
@@ -1068,7 +1068,7 @@ __STATIC_FORCEINLINE void __ECLIC_SetPriorityIRQ_S(IRQn_Type IRQn, uint8_t pri)
     uint8_t nlbits = __ECLIC_GetCfgNlbits();
     uint8_t intctlbits = (uint8_t)__ECLIC_INTCTLBITS;
     if (nlbits < intctlbits) {
-        uint8_t maxpri = ((1 << (intctlbits - nlbits)) - 1);
+        uint8_t maxpri = ((1UL << (intctlbits - nlbits)) - 1);
         if (pri > maxpri) {
             pri = maxpri;
         }
diff --git a/NMSIS/Core/Include/core_feature_plic.h b/NMSIS/Core/Include/core_feature_plic.h
@@ -155,7 +155,7 @@ __STATIC_FORCEINLINE void PLIC_EnableContextInterrupt(uint32_t ctxid, uint32_t s
     volatile uint32_t *enable_reg = (uint32_t *)PLIC_ENABLE_REGADDR(ctxid, source);
 
     uint32_t current = *enable_reg;
-    current = current | (1 << (source & 0x1F));
+    current = current | (1UL << (source & 0x1F));
     *enable_reg = current;
 }
 
@@ -174,7 +174,7 @@ __STATIC_FORCEINLINE void PLIC_DisableContextInterrupt(uint32_t ctxid, uint32_t
     volatile uint32_t *enable_reg = (uint32_t *)PLIC_ENABLE_REGADDR(ctxid, source);
 
     uint32_t current = *enable_reg;
-    current = current & (~(1 << (source & 0x1F)));
+    current = current & (~(1UL << (source & 0x1F)));
     *enable_reg = current;
 }
 
@@ -214,7 +214,7 @@ __STATIC_FORCEINLINE void PLIC_SetInterruptPending(uint32_t source)
     volatile uint32_t *pending_reg = (uint32_t *)PLIC_PENDING_REGADDR(source);
 
     uint32_t current = *pending_reg;
-    current = current | (1 << (source & 0x1F));
+    current = current | (1UL << (source & 0x1F));
     *pending_reg = current;
 }
 
@@ -233,7 +233,7 @@ __STATIC_FORCEINLINE void PLIC_ClearInterruptPending(uint32_t source)
     volatile uint32_t *pending_reg = (uint32_t *)PLIC_PENDING_REGADDR(source);
 
     uint32_t current = *pending_reg;
-    current = current & (~(1 << (source & 0x1F)));
+    current = current & (~(1UL << (source & 0x1F)));
     *pending_reg = current;
 }
 
diff --git a/NMSIS/Core/Include/core_feature_pma.h b/NMSIS/Core/Include/core_feature_pma.h
@@ -50,11 +50,11 @@
  *   @{
  */
 
-#define PMA_REGION_TYPE_SECSHARE      (0x1 << 3)    /*!< Set this region shareable between secure world and non-secure world, or else default is invalid */
-#define PMA_REGION_TYPE_NC            (0x1 << 2)    /*!< Set this region Non-Cacheable, or else default is invalid */
-#define PMA_REGION_TYPE_DEV           (0x1 << 1)    /*!< Set this region Device, or else default is invalid */
+#define PMA_REGION_TYPE_SECSHARE      (1UL << 3)    /*!< Set this region shareable between secure world and non-secure world, or else default is invalid */
+#define PMA_REGION_TYPE_NC            (1UL << 2)    /*!< Set this region Non-Cacheable, or else default is invalid */
+#define PMA_REGION_TYPE_DEV           (1UL << 1)    /*!< Set this region Device, or else default is invalid */
 #define PMA_REGION_TYPE_CA            (0)           /*!< Set this region Cacheable, which is default */
-#define PMA_REGION_ENA                (0x1 << 0)    /*!< Enable this region, then the region type will take effect */
+#define PMA_REGION_ENA                (1UL << 0)    /*!< Enable this region, then the region type will take effect */
 #define PMA_REGION_DIS                (0)           /*!< Disable this region */
 
 typedef struct PMA_CONFIG {

Original file line number	Diff line number	Diff line change
`@@ -881,7 +881,7 @@ __STATIC_FORCEINLINE void __disable_sw_irq(void)`
`881`	`881`	`*/`
`882`	`882`	`__STATIC_FORCEINLINE void __disable_core_irq(uint32_t irq)`
`883`	`883`	`{`
`884`		`- __RV_CSR_CLEAR(CSR_MIE, 1 << irq);`
	`884`	`+ __RV_CSR_CLEAR(CSR_MIE, 1UL << irq);`
`885`	`885`	`}`
`886`	`886`
`887`	`887`	`/**`
`@@ -892,7 +892,7 @@ __STATIC_FORCEINLINE void __disable_core_irq(uint32_t irq)`
`892`	`892`	`*/`
`893`	`893`	`__STATIC_FORCEINLINE void __enable_core_irq(uint32_t irq)`
`894`	`894`	`{`
`895`		`- __RV_CSR_SET(CSR_MIE, 1 << irq);`
	`895`	`+ __RV_CSR_SET(CSR_MIE, 1UL << irq);`
`896`	`896`	`}`
`897`	`897`
`898`	`898`	`/**`
`@@ -914,7 +914,7 @@ __STATIC_FORCEINLINE uint32_t __get_core_irq_pending(uint32_t irq)`
`914`	`914`	`*/`
`915`	`915`	`__STATIC_FORCEINLINE void __clear_core_irq_pending(uint32_t irq)`
`916`	`916`	`{`
`917`		`- __RV_CSR_CLEAR(CSR_MIP, 1 << irq);`
	`917`	`+ __RV_CSR_CLEAR(CSR_MIP, 1UL << irq);`
`918`	`918`	`}`
`919`	`919`
`920`	`920`	`/**`
`@@ -1013,7 +1013,7 @@ __STATIC_FORCEINLINE void __disable_sw_irq_s(void)`
`1013`	`1013`	`*/`
`1014`	`1014`	`__STATIC_FORCEINLINE void __disable_core_irq_s(uint32_t irq)`
`1015`	`1015`	`{`
`1016`		`- __RV_CSR_CLEAR(CSR_SIE, 1 << irq);`
	`1016`	`+ __RV_CSR_CLEAR(CSR_SIE, 1UL << irq);`
`1017`	`1017`	`}`
`1018`	`1018`
`1019`	`1019`	`/**`
`@@ -1024,7 +1024,7 @@ __STATIC_FORCEINLINE void __disable_core_irq_s(uint32_t irq)`
`1024`	`1024`	`*/`
`1025`	`1025`	`__STATIC_FORCEINLINE void __enable_core_irq_s(uint32_t irq)`
`1026`	`1026`	`{`
`1027`		`- __RV_CSR_SET(CSR_SIE, 1 << irq);`
	`1027`	`+ __RV_CSR_SET(CSR_SIE, 1UL << irq);`
`1028`	`1028`	`}`
`1029`	`1029`
`1030`	`1030`	`/**`
`@@ -1046,7 +1046,7 @@ __STATIC_FORCEINLINE uint32_t __get_core_irq_pending_s(uint32_t irq)`
`1046`	`1046`	`*/`
`1047`	`1047`	`__STATIC_FORCEINLINE void __clear_core_irq_pending_s(uint32_t irq)`
`1048`	`1048`	`{`
`1049`		`- __RV_CSR_CLEAR(CSR_SIP, 1 << irq);`
	`1049`	`+ __RV_CSR_CLEAR(CSR_SIP, 1UL << irq);`
`1050`	`1050`	`}`
`1051`	`1051`
`1052`	`1052`	`/**`
`@@ -1463,7 +1463,7 @@ __STATIC_FORCEINLINE void __disable_minstret_counter(void)`
`1463`	`1463`	`*/`
`1464`	`1464`	`__STATIC_FORCEINLINE void __enable_mhpm_counter(unsigned long idx)`
`1465`	`1465`	`{`
`1466`		`- __RV_CSR_CLEAR(CSR_MCOUNTINHIBIT, (1 << idx));`
	`1466`	`+ __RV_CSR_CLEAR(CSR_MCOUNTINHIBIT, (1UL << idx));`
`1467`	`1467`	`}`
`1468`	`1468`
`1469`	`1469`	`/**`
`@@ -1474,7 +1474,7 @@ __STATIC_FORCEINLINE void __enable_mhpm_counter(unsigned long idx)`
`1474`	`1474`	`*/`
`1475`	`1475`	`__STATIC_FORCEINLINE void __disable_mhpm_counter(unsigned long idx)`
`1476`	`1476`	`{`
`1477`		`- __RV_CSR_SET(CSR_MCOUNTINHIBIT, (1 << idx));`
	`1477`	`+ __RV_CSR_SET(CSR_MCOUNTINHIBIT, (1UL << idx));`
`1478`	`1478`	`}`
`1479`	`1479`
`1480`	`1480`	`/**`
Original file line number	Diff line number	Diff line change
`@@ -652,7 +652,7 @@ __STATIC_FORCEINLINE void __ECLIC_SetLevelIRQ(IRQn_Type IRQn, uint8_t lvl_abs)`
`652`	`652`	`if (nlbits > intctlbits) {`
`653`	`653`	`nlbits = intctlbits;`
`654`	`654`	`}`
`655`		`- uint8_t maxlvl = ((1 << nlbits) - 1);`
	`655`	`+ uint8_t maxlvl = ((1UL << nlbits) - 1);`
`656`	`656`	`if (lvl_abs > maxlvl) {`
`657`	`657`	`lvl_abs = maxlvl;`
`658`	`658`	`}`
`@@ -710,7 +710,7 @@ __STATIC_FORCEINLINE void __ECLIC_SetPriorityIRQ(IRQn_Type IRQn, uint8_t pri)`
`710`	`710`	`uint8_t nlbits = __ECLIC_GetCfgNlbits();`
`711`	`711`	`uint8_t intctlbits = (uint8_t)__ECLIC_INTCTLBITS;`
`712`	`712`	`if (nlbits < intctlbits) {`
`713`		`- uint8_t maxpri = ((1 << (intctlbits - nlbits)) - 1);`
	`713`	`+ uint8_t maxpri = ((1UL << (intctlbits - nlbits)) - 1);`
`714`	`714`	`if (pri > maxpri) {`
`715`	`715`	`pri = maxpri;`
`716`	`716`	`}`
`@@ -1009,7 +1009,7 @@ __STATIC_FORCEINLINE void __ECLIC_SetLevelIRQ_S(IRQn_Type IRQn, uint8_t lvl_abs)`
`1009`	`1009`	`if (nlbits > intctlbits) {`
`1010`	`1010`	`nlbits = intctlbits;`
`1011`	`1011`	`}`
`1012`		`- uint8_t maxlvl = ((1 << nlbits) - 1);`
	`1012`	`+ uint8_t maxlvl = ((1UL << nlbits) - 1);`
`1013`	`1013`	`if (lvl_abs > maxlvl) {`
`1014`	`1014`	`lvl_abs = maxlvl;`
`1015`	`1015`	`}`
`@@ -1068,7 +1068,7 @@ __STATIC_FORCEINLINE void __ECLIC_SetPriorityIRQ_S(IRQn_Type IRQn, uint8_t pri)`
`1068`	`1068`	`uint8_t nlbits = __ECLIC_GetCfgNlbits();`
`1069`	`1069`	`uint8_t intctlbits = (uint8_t)__ECLIC_INTCTLBITS;`
`1070`	`1070`	`if (nlbits < intctlbits) {`
`1071`		`- uint8_t maxpri = ((1 << (intctlbits - nlbits)) - 1);`
	`1071`	`+ uint8_t maxpri = ((1UL << (intctlbits - nlbits)) - 1);`
`1072`	`1072`	`if (pri > maxpri) {`
`1073`	`1073`	`pri = maxpri;`
`1074`	`1074`	`}`