|
49 | 49 | reg = <0>; |
50 | 50 | status = "okay"; |
51 | 51 | compatible = "riscv"; |
52 | | - riscv,isa = "rv64imafdc_zicbom_svpbmt_sstc"; |
| 52 | + riscv,isa = "rv64imafdcvh_zicbom_svpbmt_sstc"; |
53 | 53 | riscv,cbom-block-size =<64>; |
54 | 54 | mmu-type = "riscv,sv39"; |
55 | 55 | clock-frequency = <CPUCLK_FREQ>; |
|
64 | 64 | reg = <1>; |
65 | 65 | status = "okay"; |
66 | 66 | compatible = "riscv"; |
67 | | - riscv,isa = "rv64imafdc_zicbom_svpbmt_sstc"; |
| 67 | + riscv,isa = "rv64imafdcvh_zicbom_svpbmt_sstc"; |
68 | 68 | riscv,cbom-block-size =<64>; |
69 | 69 | mmu-type = "riscv,sv39"; |
70 | 70 | clock-frequency = <CPUCLK_FREQ>; |
|
79 | 79 | reg = <2>; |
80 | 80 | status = "okay"; |
81 | 81 | compatible = "riscv"; |
82 | | - riscv,isa = "rv64imafdc_zicbom_svpbmt_sstc"; |
| 82 | + riscv,isa = "rv64imafdcvh_zicbom_svpbmt_sstc"; |
83 | 83 | riscv,cbom-block-size =<64>; |
84 | 84 | mmu-type = "riscv,sv39"; |
85 | 85 | clock-frequency = <CPUCLK_FREQ>; |
|
94 | 94 | reg = <3>; |
95 | 95 | status = "okay"; |
96 | 96 | compatible = "riscv"; |
97 | | - riscv,isa = "rv64imafdc_zicbom_svpbmt_sstc"; |
| 97 | + riscv,isa = "rv64imafdcvh_zicbom_svpbmt_sstc"; |
98 | 98 | riscv,cbom-block-size =<64>; |
99 | 99 | mmu-type = "riscv,sv39"; |
100 | 100 | clock-frequency = <CPUCLK_FREQ>; |
|
109 | 109 | reg = <4>; |
110 | 110 | status = "okay"; |
111 | 111 | compatible = "riscv"; |
112 | | - riscv,isa = "rv64imafdc_zicbom_svpbmt_sstc"; |
| 112 | + riscv,isa = "rv64imafdcvh_zicbom_svpbmt_sstc"; |
113 | 113 | riscv,cbom-block-size =<64>; |
114 | 114 | mmu-type = "riscv,sv39"; |
115 | 115 | clock-frequency = <CPUCLK_FREQ>; |
|
124 | 124 | reg = <5>; |
125 | 125 | status = "okay"; |
126 | 126 | compatible = "riscv"; |
127 | | - riscv,isa = "rv64imafdc_zicbom_svpbmt_sstc"; |
| 127 | + riscv,isa = "rv64imafdcvh_zicbom_svpbmt_sstc"; |
128 | 128 | riscv,cbom-block-size =<64>; |
129 | 129 | mmu-type = "riscv,sv39"; |
130 | 130 | clock-frequency = <CPUCLK_FREQ>; |
|
139 | 139 | reg = <6>; |
140 | 140 | status = "okay"; |
141 | 141 | compatible = "riscv"; |
142 | | - riscv,isa = "rv64imafdc_zicbom_svpbmt_sstc"; |
| 142 | + riscv,isa = "rv64imafdcvh_zicbom_svpbmt_sstc"; |
143 | 143 | riscv,cbom-block-size =<64>; |
144 | 144 | mmu-type = "riscv,sv39"; |
145 | 145 | clock-frequency = <CPUCLK_FREQ>; |
|
154 | 154 | reg = <7>; |
155 | 155 | status = "okay"; |
156 | 156 | compatible = "riscv"; |
157 | | - riscv,isa = "rv64imafdc_zicbom_svpbmt_sstc"; |
| 157 | + riscv,isa = "rv64imafdcvh_zicbom_svpbmt_sstc"; |
158 | 158 | riscv,cbom-block-size =<64>; |
159 | 159 | mmu-type = "riscv,sv39"; |
160 | 160 | clock-frequency = <CPUCLK_FREQ>; |
|
399 | 399 | phy-handle = <&rtl8211f>; |
400 | 400 | phy-mode = "rgmii"; |
401 | 401 |
|
402 | | - status = "disabled"; |
| 402 | + status = "okay"; |
403 | 403 | mdio { |
404 | 404 | compatible = "snps,dwmac-mdio"; |
405 | 405 | #address-cells = <1>; |
|
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