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conf/evalsoc: update dts for nuclei pmu version 2
Now we support pmu v2 in perf tool, and perf rv32 tool is also supported, see #26 Signed-off-by: Huaqi Fang <[email protected]>
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‎conf/evalsoc/nuclei_rv32imac.dts‎

Lines changed: 246 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -182,6 +182,252 @@
182182
clock-output-names = "hfclk";
183183
};
184184

185+
pmu {
186+
compatible = "riscv,pmu";
187+
/* https://perf.wiki.kernel.org/index.php/Tutorial#Events */
188+
/* eg. perf stat -B coremark */
189+
/* eg. perf stat -e cycles -e instructions -e cache-misses -e branches -e branch-misses coremark */
190+
/* eg. perf stat -e cycles -e instructions -e L1-icache-load-misses -e L1-dcache-load-misses -e iTLB-load-misses -e dTLB-load-misses coremark */
191+
/* Note: in the dts comment, v2 means your Nuclei RISC-V CPU need to support HPM_VER = Version 2 */
192+
riscv,event-to-mhpmevent =
193+
/* Type #0 SBI_PMU_HW_CPU_CYCLES -> Nuclei event sel=0 idx=1 Cycle count */
194+
<0x00001 0x00000000 0x00000010>,
195+
/* Type #0 SBI_PMU_HW_INSTRUCTIONS -> Nuclei event sel=0 idx=2 Retired instruction count */
196+
<0x00002 0x00000000 0x00000020>,
197+
/* Type #0 SBI_PMU_HW_CACHE_REFERENCES -> v2, Nuclei event sel=1 idx=8 L2-Cache access count */
198+
<0x00003 0x00000000 0x00000081>,
199+
/* Type #0 SBI_PMU_HW_CACHE_MISSES -> v2, Nuclei event sel=1 idx=9 L2-Cache miss count */
200+
<0x00004 0x00000000 0x00000091>,
201+
/* Type #0 SBI_PMU_HW_BRANCH_INSTRUCTIONS -> v2, Nuclei event sel=2 idx=2 Branch instruction commit count */
202+
<0x00005 0x00000000 0x00000022>,
203+
/* Type #0 SBI_PMU_HW_BRANCH_MISSES -> v2, Nuclei event sel=2 idx=3 Branch predict fail count */
204+
<0x00006 0x00000000 0x00000032>,
205+
/* Type #0 SBI_PMU_HW_BUS_CYCLES -> v2, Nuclei event sel=1 idx=10 Memory bus request count */
206+
<0x00007 0x00000000 0x000000A1>,
207+
/* Type #0 SBI_PMU_HW_STALLED_CYCLES_FRONTEND -> v2, Nuclei event sel=1 idx=11 IFU stall cycle count */
208+
<0x00008 0x00000000 0x000000B1>,
209+
/* Type #0 SBI_PMU_HW_STALLED_CYCLES_BACKEND -> v2, Nuclei event sel=1 idx=12 EXU stall cycle count */
210+
<0x00009 0x00000000 0x000000C1>,
211+
/* Type #0 SBI_PMU_HW_REF_CPU_CYCLES -> v2, Nuclei event sel=1 idx=13 Timer count */
212+
<0x0000A 0x00000000 0x000000D1>,
213+
/* Type #1 SBI_PMU_HW_CACHE_L1D(0) READ(0) ACCESS(0) -> v2, Nuclei event sel=3 idx=0 Dcache read count */
214+
<0x10000 0x00000000 0x00000003>,
215+
/* Type #1 SBI_PMU_HW_CACHE_L1D(0) READ(0) MISS(1) -> v2, Nuclei event sel=3 idx=1 Dcache read miss count */
216+
<0x10001 0x00000000 0x00000013>,
217+
/* Type #1 SBI_PMU_HW_CACHE_L1D(0) WRITE(1) ACCESS(0) -> v2, Nuclei event sel=3 idx=2 Dcache write count */
218+
<0x10002 0x00000000 0x00000023>,
219+
/* Type #1 SBI_PMU_HW_CACHE_L1D(0) WRITE(1) MISS(1) -> v2, Nuclei event sel=3 idx=3 Dcache write miss count */
220+
<0x10003 0x00000000 0x00000033>,
221+
/* Type #1 SBI_PMU_HW_CACHE_L1D(0) PREFETCH(2) ACCESS(0) -> v2, Nuclei event sel=3 idx=4 Dcache prefetch count */
222+
<0x10004 0x00000000 0x00000043>,
223+
/* Type #1 SBI_PMU_HW_CACHE_L1D(0) PREFETCH(2) MISS(1) -> v2, Nuclei event sel=3 idx=5 Dcache prefetch miss count */
224+
<0x10005 0x00000000 0x00000053>,
225+
/* Type #1 SBI_PMU_HW_CACHE_L1I(1) READ(0) ACCESS(0) -> v2, Nuclei event sel=3 idx=6 Icache read count */
226+
<0x10008 0x00000000 0x00000063>,
227+
/* Type #1 SBI_PMU_HW_CACHE_L1I(1) READ(0) MISS(1) -> v1, Nuclei event sel=1 idx=1 Icache read miss count */
228+
<0x10009 0x00000000 0x00000011>,
229+
/* Type #1 SBI_PMU_HW_CACHE_L1I(1) PREFETCH(2) ACCESS(0) -> v2, Nuclei event sel=3 idx=8 Icache prefetch count */
230+
<0x1000C 0x00000000 0x00000083>,
231+
/* Type #1 SBI_PMU_HW_CACHE_L1I(1) PREFETCH(2) MISS(1) -> v2, Nuclei event sel=3 idx=9 Icache prefetch miss count */
232+
<0x1000D 0x00000000 0x00000093>,
233+
/* Type #1 SBI_PMU_HW_CACHE_LL(2) READ(0) ACCESS(0) -> v2, Nuclei event sel=3 idx=10 L2 Cache read count */
234+
<0x10010 0x00000000 0x000000A3>,
235+
/* Type #1 SBI_PMU_HW_CACHE_LL(2) READ(0) MISS(1) -> v2, Nuclei event sel=3 idx=11 L2 Cache read miss count */
236+
<0x10011 0x00000000 0x000000B3>,
237+
/* Type #1 SBI_PMU_HW_CACHE_LL(2) WRITE(1) ACCESS(0) -> v2, Nuclei event sel=3 idx=12 L2 Cache write count */
238+
<0x10012 0x00000000 0x000000C3>,
239+
/* Type #1 SBI_PMU_HW_CACHE_LL(2) WRITE(1) MISS(1) -> v2, Nuclei event sel=3 idx=13 L2 Cache write miss count */
240+
<0x10013 0x00000000 0x000000D3>,
241+
/* Type #1 SBI_PMU_HW_CACHE_LL(2) PREFETCH(2) ACCESS(0) -> v2, Nuclei event sel=3 idx=14 L2 Cache prefetch count */
242+
<0x10014 0x00000000 0x000000E3>,
243+
/* Type #1 SBI_PMU_HW_CACHE_LL(2) PREFETCH(2) MISS(1) -> v2, Nuclei event sel=3 idx=15 L2 Cache prefetch miss count */
244+
<0x10015 0x00000000 0x000000F3>,
245+
/* Type #1 SBI_PMU_HW_CACHE_DTLB(3) READ(0) ACCESS(0) -> v2, Nuclei event sel=3 idx=16 DTLB read count */
246+
<0x10018 0x00000000 0x00000103>,
247+
/* Type #1 SBI_PMU_HW_CACHE_DTLB(3) READ(0) MISS(1) -> v2, Nuclei event sel=3 idx=17 DTLB read miss count */
248+
<0x10019 0x00000000 0x00000113>,
249+
/* Type #1 SBI_PMU_HW_CACHE_DTLB(3) WRITE(1) ACCESS(0) -> v2, Nuclei event sel=3 idx=18 DTLB write count */
250+
<0x1001A 0x00000000 0x00000123>,
251+
/* Type #1 SBI_PMU_HW_CACHE_DTLB(3) WRITE(1) MISS(1) -> v2, Nuclei event sel=3 idx=19 DTLB write miss count */
252+
<0x1001B 0x00000000 0x00000133>,
253+
/* Type #1 SBI_PMU_HW_CACHE_ITLB(4) READ(0) ACCESS(0) -> v2, Nuclei event sel=3 idx=20 ITLB read count */
254+
<0x10020 0x00000000 0x00000143>,
255+
/* Type #1 SBI_PMU_HW_CACHE_ITLB(4) READ(0) MISS(1) -> v1, Nuclei event sel=1 idx=3 ITLB read miss count */
256+
<0x10021 0x00000000 0x00000031>,
257+
/* Type #1 SBI_PMU_HW_CACHE_BTB(5) READ(0) ACCESS(0) -> v2, Nuclei event sel=3 idx=22 BTB read count */
258+
<0x10028 0x00000000 0x00000163>,
259+
/* Type #1 SBI_PMU_HW_CACHE_BTB(5) READ(0) MISS(1) -> v2, Nuclei event sel=3 idx=23 BTB read miss count */
260+
<0x10029 0x00000000 0x00000173>,
261+
/* Type #1 SBI_PMU_HW_CACHE_BTB(5) WRITE(1) ACCESS(0) -> v2, Nuclei event sel=3 idx=24 BTB write count */
262+
<0x1002A 0x00000000 0x00000183>,
263+
/* Type #1 SBI_PMU_HW_CACHE_BTB(5) WRITE(1) MISS(1) -> v2, Nuclei event sel=3 idx=25 BTB write miss count */
264+
<0x1002B 0x00000000 0x00000193>,
265+
/* Type #1 SBI_PMU_HW_CACHE_NODE(6) READ(0) ACCESS(0) -> v2, Nuclei event sel=3 idx=10 L2 Cache read count */
266+
<0x10030 0x00000000 0x000000A3>,
267+
/* Type #1 SBI_PMU_HW_CACHE_NODE(6) READ(0) MISS(1) -> v2, Nuclei event sel=3 idx=11 L2 Cache read miss count */
268+
<0x10031 0x00000000 0x000000B3>,
269+
/* Type #1 SBI_PMU_HW_CACHE_NODE(6) WRITE(1) ACCESS(0) -> v2, Nuclei event sel=3 idx=12 L2 Cache write count */
270+
<0x10032 0x00000000 0x000000C3>,
271+
/* Type #1 SBI_PMU_HW_CACHE_NODE(6) WRITE(1) MISS(1) -> v2, Nuclei event sel=3 idx=13 L2 Cache write miss count */
272+
<0x10033 0x00000000 0x000000D3>,
273+
/* Type #1 SBI_PMU_HW_CACHE_NODE(6) PREFETCH(2) ACCESS(0) -> v2, Nuclei event sel=3 idx=14 L2 Cache prefetch count */
274+
<0x10034 0x00000000 0x000000E3>,
275+
/* Type #1 SBI_PMU_HW_CACHE_NODE(6) PREFETCH(2) MISS(1) -> v2, Nuclei event sel=3 idx=15 L2 Cache prefetch miss count */
276+
<0x10035 0x00000000 0x000000F3>;
277+
/* make hpm3-6 counter available for all hardware events */
278+
riscv,event-to-mhpmcounters =
279+
<0x00001 0x0000000A 0x00000078>,
280+
<0x10000 0x00010035 0x00000078>;
281+
/* Raw event: eg. perf stat -e cycles -e instructions -e r00000190 -e r00000010 coremark */
282+
riscv,raw-event-to-mhpmcounters =
283+
/* Event Types 0 events - 0x1 Cycle count */
284+
<0x00000000 0x00000010 0xffffffff 0xffffffff 0x00000078>,
285+
/* Event Types 0 events - 0x2 Retired instruction count */
286+
<0x00000000 0x00000020 0xffffffff 0xffffffff 0x00000078>,
287+
/* Event Types 0 events - 0x3 Integer load instruction (includes LR) */
288+
<0x00000000 0x00000030 0xffffffff 0xffffffff 0x00000078>,
289+
/* Event Types 0 events - 0x4 Integer store instruction (includes SC) */
290+
<0x00000000 0x00000040 0xffffffff 0xffffffff 0x00000078>,
291+
/* Event Types 0 events - 0x5 Atomic memory operation (do not include LR and SC) */
292+
<0x00000000 0x00000050 0xffffffff 0xffffffff 0x00000078>,
293+
/* Event Types 0 events - 0x6 System instruction */
294+
<0x00000000 0x00000060 0xffffffff 0xffffffff 0x00000078>,
295+
/* Event Types 0 events - 0x7 Integer computational instruction(excluding multiplication/division/remainder) */
296+
<0x00000000 0x00000070 0xffffffff 0xffffffff 0x00000078>,
297+
/* Event Types 0 events - 0x8 Conditional branch */
298+
<0x00000000 0x00000080 0xffffffff 0xffffffff 0x00000078>,
299+
/* Event Types 0 events - 0x9 Taken conditional branch */
300+
<0x00000000 0x00000090 0xffffffff 0xffffffff 0x00000078>,
301+
/* Event Types 0 events - 0xa JAL instruction */
302+
<0x00000000 0x000000a0 0xffffffff 0xffffffff 0x00000078>,
303+
/* Event Types 0 events - 0xb JALR instruction */
304+
<0x00000000 0x000000b0 0xffffffff 0xffffffff 0x00000078>,
305+
/* Event Types 0 events - 0xc Return instruction */
306+
<0x00000000 0x000000c0 0xffffffff 0xffffffff 0x00000078>,
307+
/* Event Types 0 events - 0xd Control transfer instruction (CBR+JAL+JALR) */
308+
<0x00000000 0x000000d0 0xffffffff 0xffffffff 0x00000078>,
309+
/* Event Types 0 events - 0xe fence instruction(Not include fence.i) */
310+
<0x00000000 0x000000e0 0xffffffff 0xffffffff 0x00000078>,
311+
/* Event Types 0 events - 0xf Integer multiplication instruction */
312+
<0x00000000 0x000000f0 0xffffffff 0xffffffff 0x00000078>,
313+
/* Event Types 0 events - 0x10 Integer division/remainder instruction */
314+
<0x00000000 0x00000100 0xffffffff 0xffffffff 0x00000078>,
315+
/* Event Types 0 events - 0x11 Floating-point load instruction */
316+
<0x00000000 0x00000110 0xffffffff 0xffffffff 0x00000078>,
317+
/* Event Types 0 events - 0x12 Floating-point store instruction */
318+
<0x00000000 0x00000120 0xffffffff 0xffffffff 0x00000078>,
319+
/* Event Types 0 events - 0x13 Floating-point addition/subtraction */
320+
<0x00000000 0x00000130 0xffffffff 0xffffffff 0x00000078>,
321+
/* Event Types 0 events - 0x14 Floating-point multiplication */
322+
<0x00000000 0x00000140 0xffffffff 0xffffffff 0x00000078>,
323+
/* Event Types 0 events - 0x15 Floating-point fused multiply-add (FMADD, FMSUB,FNMSUB, FNMADD) */
324+
<0x00000000 0x00000150 0xffffffff 0xffffffff 0x00000078>,
325+
/* Event Types 0 events - 0x16 Floating-point division or square-root */
326+
<0x00000000 0x00000160 0xffffffff 0xffffffff 0x00000078>,
327+
/* Event Types 0 events - 0x17 Other floating-point instruction */
328+
<0x00000000 0x00000170 0xffffffff 0xffffffff 0x00000078>,
329+
/* Event Types 0 events - 0x18 Conditional branch(BXX) prediction fail */
330+
<0x00000000 0x00000180 0xffffffff 0xffffffff 0x00000078>,
331+
/* Event Types 0 events - 0x19 JALR prediction fail */
332+
<0x00000000 0x00000190 0xffffffff 0xffffffff 0x00000078>,
333+
/* Event Types 0 events - 0x1a POP prediction fail */
334+
<0x00000000 0x000001a0 0xffffffff 0xffffffff 0x00000078>,
335+
/* Event Types 0 events - 0x1b FENCEI instruction */
336+
<0x00000000 0x000001b0 0xffffffff 0xffffffff 0x00000078>,
337+
/* Event Types 0 events - 0x1c SFENCE instruction */
338+
<0x00000000 0x000001c0 0xffffffff 0xffffffff 0x00000078>,
339+
/* Event Types 0 events - 0x1d ECALL instruction */
340+
<0x00000000 0x000001d0 0xffffffff 0xffffffff 0x00000078>,
341+
/* Event Types 0 events - 0x1e EXCEPTION instruction */
342+
<0x00000000 0x000001e0 0xffffffff 0xffffffff 0x00000078>,
343+
/* Event Types 0 events - 0x1f INTERRUPT instruction */
344+
<0x00000000 0x000001f0 0xffffffff 0xffffffff 0x00000078>,
345+
/* Event Types 1 events - 0x1 Icache read miss count */
346+
<0x00000000 0x00000011 0xffffffff 0xffffffff 0x00000078>,
347+
/* Event Types 1 events - 0x2 Dcache read/write miss count */
348+
<0x00000000 0x00000021 0xffffffff 0xffffffff 0x00000078>,
349+
/* Event Types 1 events - 0x3 ITLB read miss count */
350+
<0x00000000 0x00000031 0xffffffff 0xffffffff 0x00000078>,
351+
/* Event Types 1 events - 0x4 DTLB read/write miss count */
352+
<0x00000000 0x00000041 0xffffffff 0xffffffff 0x00000078>,
353+
/* Event Types 1 events - 0x5 Main TLB miss count */
354+
<0x00000000 0x00000051 0xffffffff 0xffffffff 0x00000078>,
355+
/* Event Types 1 events - 0x6 Reserved */
356+
<0x00000000 0x00000061 0xffffffff 0xffffffff 0x00000078>,
357+
/* Event Types 1 events - 0x7 Reserved */
358+
<0x00000000 0x00000071 0xffffffff 0xffffffff 0x00000078>,
359+
/* Event Types 1 events - 0x8 L2-Cache access count */
360+
<0x00000000 0x00000081 0xffffffff 0xffffffff 0x00000078>,
361+
/* Event Types 1 events - 0x9 L2-Cache miss count */
362+
<0x00000000 0x00000091 0xffffffff 0xffffffff 0x00000078>,
363+
/* Event Types 1 events - 0xa Memory bus request count */
364+
<0x00000000 0x000000a1 0xffffffff 0xffffffff 0x00000078>,
365+
/* Event Types 1 events - 0xb IFU stall cycle count */
366+
<0x00000000 0x000000b1 0xffffffff 0xffffffff 0x00000078>,
367+
/* Event Types 1 events - 0xc EXU stall cycle count */
368+
<0x00000000 0x000000c1 0xffffffff 0xffffffff 0x00000078>,
369+
/* Event Types 1 events - 0xd Timer count */
370+
<0x00000000 0x000000d1 0xffffffff 0xffffffff 0x00000078>,
371+
/* Event Types 2 events - 0x1 VPU store instruction commit count */
372+
<0x00000000 0x00000012 0xffffffff 0xffffffff 0x00000078>,
373+
/* Event Types 2 events - 0x2 Reserved */
374+
<0x00000000 0x00000022 0xffffffff 0xffffffff 0x00000078>,
375+
/* Event Types 2 events - 0x3 VPU load instruction commit count */
376+
<0x00000000 0x00000032 0xffffffff 0xffffffff 0x00000078>,
377+
/* Event Types 2 events - 0x4 VPU computational instruction commit count */
378+
<0x00000000 0x00000042 0xffffffff 0xffffffff 0x00000078>,
379+
/* Event Types 2 events - 0x5 Branch predict fail count */
380+
<0x00000000 0x00000052 0xffffffff 0xffffffff 0x00000078>,
381+
/* Event Types 3 events - 0x1 Icache read count */
382+
<0x00000000 0x00000013 0xffffffff 0xffffffff 0x00000078>,
383+
/* Event Types 3 events - 0x2 L2-Cache read hit count */
384+
<0x00000000 0x00000023 0xffffffff 0xffffffff 0x00000078>,
385+
/* Event Types 3 events - 0x3 DTLB write count */
386+
<0x00000000 0x00000033 0xffffffff 0xffffffff 0x00000078>,
387+
/* Event Types 3 events - 0x4 L2-Cache write miss count */
388+
<0x00000000 0x00000043 0xffffffff 0xffffffff 0x00000078>,
389+
/* Event Types 3 events - 0x5 Reserved */
390+
<0x00000000 0x00000053 0xffffffff 0xffffffff 0x00000078>,
391+
/* Event Types 3 events - 0x6 Icache prefetch miss count */
392+
<0x00000000 0x00000063 0xffffffff 0xffffffff 0x00000078>,
393+
/* Event Types 3 events - 0x7 BTB write count */
394+
<0x00000000 0x00000073 0xffffffff 0xffffffff 0x00000078>,
395+
/* Event Types 3 events - 0x8 L2-Cache read miss count */
396+
<0x00000000 0x00000083 0xffffffff 0xffffffff 0x00000078>,
397+
/* Event Types 3 events - 0x9 DTLB write miss count */
398+
<0x00000000 0x00000093 0xffffffff 0xffffffff 0x00000078>,
399+
/* Event Types 3 events - 0xa ITLB read count */
400+
<0x00000000 0x000000a3 0xffffffff 0xffffffff 0x00000078>,
401+
/* Event Types 3 events - 0xb BTB read count */
402+
<0x00000000 0x000000b3 0xffffffff 0xffffffff 0x00000078>,
403+
/* Event Types 3 events - 0xc Dcache prefetch count */
404+
<0x00000000 0x000000c3 0xffffffff 0xffffffff 0x00000078>,
405+
/* Event Types 3 events - 0xd Icache prefetch count */
406+
<0x00000000 0x000000d3 0xffffffff 0xffffffff 0x00000078>,
407+
/* Event Types 3 events - 0xe Dcache write count */
408+
<0x00000000 0x000000e3 0xffffffff 0xffffffff 0x00000078>,
409+
/* Event Types 3 events - 0xf DTLB read count */
410+
<0x00000000 0x000000f3 0xffffffff 0xffffffff 0x00000078>,
411+
/* Event Types 3 events - 0x10 Dcache write miss count */
412+
<0x00000000 0x00000103 0xffffffff 0xffffffff 0x00000078>,
413+
/* Event Types 3 events - 0x11 BTB write miss count */
414+
<0x00000000 0x00000113 0xffffffff 0xffffffff 0x00000078>,
415+
/* Event Types 3 events - 0x12 Dcache read count */
416+
<0x00000000 0x00000123 0xffffffff 0xffffffff 0x00000078>,
417+
/* Event Types 3 events - 0x13 L2-Cache write hit count */
418+
<0x00000000 0x00000133 0xffffffff 0xffffffff 0x00000078>,
419+
/* Event Types 3 events - 0x14 L2-Cache prefetch miss count */
420+
<0x00000000 0x00000143 0xffffffff 0xffffffff 0x00000078>,
421+
/* Event Types 3 events - 0x15 BTB read miss count */
422+
<0x00000000 0x00000153 0xffffffff 0xffffffff 0x00000078>,
423+
/* Event Types 3 events - 0x16 Dcache read miss count */
424+
<0x00000000 0x00000163 0xffffffff 0xffffffff 0x00000078>,
425+
/* Event Types 3 events - 0x17 L2-Cache prefetch hit count */
426+
<0x00000000 0x00000173 0xffffffff 0xffffffff 0x00000078>,
427+
/* Event Types 3 events - 0x18 DTLB read miss count */
428+
<0x00000000 0x00000183 0xffffffff 0xffffffff 0x00000078>;
429+
};
430+
185431
plic0: interrupt-controller@1c000000 {
186432
#interrupt-cells = <1>;
187433
compatible = "riscv,plic0";

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