OS: bugfix for RT-Thread task switch stack frame not 16 bytes aligned

Make task frame 16 bytes aligned by changing saved regs from 30 to 32

https://github.com/riscv-mcu/riscv-gcc/blob/553a166de2dd7451652a0973908e1f2459118506/gcc/config/riscv/riscv.h#L201-L211

Signed-off-by: Huaqi Fang <578567190@qq.com>

Author: fanghuaqi

OS/RTThread/libcpu/risc-v/nuclei/cpuport.c

@@ -64,6 +64,7 @@ volatile rt_ubase_t  rt_interrupt_to_thread   = 0;
 volatile rt_ubase_t rt_thread_switch_interrupt_flag = 0;
 void SysTick_Handler(void);
 
+/* Stack frame size 32 REGBYTES(4/8) for most cases, but for ilp32e mode, it's 14 REGBYTES(4) */
 struct rt_hw_stack_frame {
     rt_ubase_t epc;        /* epc - epc    - program counter                     */
     rt_ubase_t ra;         /* x1  - ra     - return address for jumps            */
@@ -95,6 +96,8 @@ struct rt_hw_stack_frame {
     rt_ubase_t t4;         /* x29 - t4     - temporary register 4                */
     rt_ubase_t t5;         /* x30 - t5     - temporary register 5                */
     rt_ubase_t t6;         /* x31 - t6     - temporary register 6                */
+    rt_ubase_t rsv0;       /* reserved 0   - reserved to make space              */
+    rt_ubase_t rsv1;       /* reserved 1   - reserved to make space              */
 #endif
     rt_ubase_t xstatus;    /*              - m/s status register             */
 };

OS/RTThread/libcpu/risc-v/nuclei/gcc/context_gcc.S

@@ -10,9 +10,12 @@
 
 #include "riscv_encoding.h"
 
+/* see https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-cc.adoc */
 #ifndef __riscv_32e
-#define portRegNum          30
+/* Make sure the stack pointer is 16-byte aligned when calling c function */
+#define portRegNum          32
 #else
+/* Make sure the stack pointer is 4-byte aligned when calling c function for ilp32e */
 #define portRegNum          14
 #endif
 
@@ -21,11 +24,8 @@
     .extern rt_interrupt_from_thread
     .extern rt_interrupt_to_thread
 
-
 .section    .text
 
-
-
 /*
  * void rt_hw_context_switch_to(rt_ubase_t to);
  * a0 --> to_thread
@@ -48,14 +48,14 @@ rt_hw_context_switch_to:
     csrw CSR_XSCRATCH, t0
     LOAD sp, 0x0(a0)                /* Read sp from first TCB member(a0) */
 
-    /* Pop PC from stack and set MEPC */
+    /* Pop PC from stack and set XEPC */
     LOAD t0,  0  * REGBYTES(sp)
     csrw CSR_XEPC, t0
-    /* Pop mstatus from stack and set it */
+    /* Pop xstatus from stack and set it */
     LOAD t0,  (portRegNum - 1)  * REGBYTES(sp)
     csrw CSR_XSTATUS, t0
     /* Interrupt still disable here */
-    /* Restore Registers from Stack */
+    /* Restore registers from stack */
     LOAD x1,  1  * REGBYTES(sp)    /* RA */
     LOAD x5,  2  * REGBYTES(sp)
     LOAD x6,  3  * REGBYTES(sp)
@@ -128,7 +128,7 @@ eclic_xsip_handler:
     STORE x30, 27 * REGBYTES(sp)
     STORE x31, 28 * REGBYTES(sp)
 #endif
-    /* Push mstatus to stack */
+    /* Push xstatus to stack */
     csrr t0, CSR_XSTATUS
     STORE t0,  (portRegNum - 1)  * REGBYTES(sp)
 
@@ -147,16 +147,16 @@ eclic_xsip_handler:
     LOAD t0, rt_interrupt_to_thread
     LOAD sp, 0x0(t0)
 
-    /* Pop PC from stack and set MEPC */
+    /* Pop PC from stack and set XEPC */
     LOAD t0,  0  * REGBYTES(sp)
     csrw CSR_XEPC, t0
     /* Pop additional registers */
 
-    /* Pop mstatus from stack and set it */
+    /* Pop xstatus from stack and set it */
     LOAD t0,  (portRegNum - 1)  * REGBYTES(sp)
     csrw CSR_XSTATUS, t0
     /* Interrupt still disable here */
-    /* Restore Registers from Stack */
+    /* Restore registers from stack */
     LOAD x1,  1  * REGBYTES(sp)    /* RA */
     LOAD x5,  2  * REGBYTES(sp)
     LOAD x6,  3  * REGBYTES(sp)

OS/RTThread/libcpu/risc-v/nuclei/iar/context_iar.S

@@ -11,7 +11,7 @@
 #include "riscv_encoding.h"
 
 #ifndef __riscv_32e
-#define portRegNum          30
+#define portRegNum          32
 #else
 #define portRegNum          14
 #endif