@@ -377,8 +377,8 @@ _save_fp_stack:
377377 LOAD t1, 1 * REGBYTES(sp)
378378 addi sp, sp, (2 * REGBYTES)
379379
380- /* Save fp registers and fcsr */
381- addi sp, sp, -(2 * REGBYTES)
380+ /* Save fp registers and fcsr and 3 reserved reg space, make sure 16 bytes aligned */
381+ addi sp, sp, -(5 * REGBYTES)
382382 STORE t0, 0 * REGBYTES(sp)
383383 csrr t0, CSR_FCSR
384384 STORE t0, 1 * REGBYTES(sp)
@@ -649,7 +649,7 @@ _restore_fp_stack:
649649 LOAD t1, 1 * REGBYTES(sp)
650650 addi sp, sp, (2 * REGBYTES)
651651
652- /* Save fp registers and fcsr */
652+ /* Restore fp registers and fcsr and 3 reserved reg space */
653653 FPLOAD f0 , 0 * FPREGBYTES(sp)
654654 FPLOAD f1 , 1 * FPREGBYTES(sp)
655655 FPLOAD f2 , 2 * FPREGBYTES(sp)
@@ -689,7 +689,7 @@ _restore_fp_stack:
689689 LOAD t0, 1 * REGBYTES(sp)
690690 csrw CSR_FCSR, t0
691691 LOAD t0, 0 * REGBYTES(sp)
692- addi sp, sp, (2 * REGBYTES)
692+ addi sp, sp, (5 * REGBYTES)
693693#endif
694694
695695#if defined(__riscv_flen) || defined(__riscv_vector)
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