SoC/evalsoc: Enable IC_CANCEL_EN by default to prevent I-cache pipeline stalls on branch misprediction

fanghuaqi · fanghuaqi · commit 7b7246a6bdaf · 2025-11-19T15:05:00.000+08:00
Signed-off-by: Huaqi Fang &lt;578567190@qq.com&gt;
diff --git a/SoC/evalsoc/Common/Source/system_evalsoc.c b/SoC/evalsoc/Common/Source/system_evalsoc.c
@@ -1424,6 +1424,8 @@ void _premain_init(void)
 #endif
 #endif
         EnableICache();
+        // Enable canceling previous accesses in icache e1 stage when change flow happens
+        __RV_CSR_SET(CSR_MCACHE_CTL, MCACHE_CTL_IC_PF_EN);
     }
 #endif
 #if defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1)
diff --git a/doc/source/changelog.rst b/doc/source/changelog.rst
@@ -63,6 +63,7 @@ This is release version of ``0.9.0`` of Nuclei SDK, which is still under develop
   - Optimize SMP bringup process, boot hart should wait for other harts software pending bit be set, mainly to be suitable
     for Nuclei Qemu 2025.10, the other harts run slow than main harts
   - Enable nuclei cpu model debug configuration generation using npk, which require Nuclei Studio and Model 2025.10 version, currently only non-smp debug is supported by Nuclei CPU Model
+  - Enable ``IC_CANCEL_EN`` in mcache_ctl when I-Cache present by default to prevent I-cache pipeline stalls on branch misprediction
 
 * Documentation
 

Original file line number	Diff line number	Diff line change
`@@ -1424,6 +1424,8 @@ void _premain_init(void)`
`1424`	`1424`	`#endif`
`1425`	`1425`	`#endif`
`1426`	`1426`	`EnableICache();`
	`1427`	`+ // Enable canceling previous accesses in icache e1 stage when change flow happens`
	`1428`	`+ __RV_CSR_SET(CSR_MCACHE_CTL, MCACHE_CTL_IC_PF_EN);`
`1427`	`1429`	`}`
`1428`	`1430`	`#endif`
`1429`	`1431`	`#if defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1)`