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doc: update changelog and expected output of cpuinfo
Signed-off-by: qiujiandong <[email protected]>
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‎doc/source/changelog.rst‎

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@@ -21,6 +21,8 @@ This is release version of ``0.9.0`` of Nuclei SDK, which is still under develop
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- Add new application :ref:`design_app_demo_eclic_umode` to show how to use U-Mode with ECLIC running in M-Mode
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- For FreeRTOS demo/smpdemo, now default use MSTATUS.MIE to do interrupt masking since default ``configMAX_SYSCALL_INTERRUPT_PRIORITY`` set to 255
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- Update ``cpuinfo`` to display additional CPU features, including prefetch capabilities, hardware performance configirations, supported ISAs, and more. See :ref:`design_app_cpuinfo`.
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- Add ``get_basic_cpuinfo`` in ``cpuinfo`` to get basic CPU information in a single string.
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* OS
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@@ -49,6 +51,7 @@ This is release version of ``0.9.0`` of Nuclei SDK, which is still under develop
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- Fix typo ``reuqests`` to ``requires`` in ``app.rst``
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- Update ``rtos.rst`` to mention about recent bugfix for RTOS porting, and other RTOSes supported but not in Nuclei SDK
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- Update the expected output of ``cpuinfo`` in ``app.rst``
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* Tools
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‎doc/source/design/app.rst‎

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@@ -130,7 +130,7 @@ You can also use openocd to probe the cpu feature, see https://doc.nucleisys.com
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# Assume that you can set up the Tools and Nuclei SDK environment
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# cd to the helloworld directory
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cd application/baremetal/cpuinfo
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# Assume to run on UX900 SMPx8 CPU
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# Assume to run on UX1030 SMPx1 RVA23 CPU
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# Clean the application first
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make SOC=evalsoc DOWNLOAD=sram clean
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# Build and upload the application
@@ -140,33 +140,99 @@ You can also use openocd to probe the cpu feature, see https://doc.nucleisys.com
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.. code-block:: console
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Nuclei SDK Build Time: May 28 2024, 13:36:12
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Nuclei SDK Build Time: Sep 23 2025, 09:41:30
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Download Mode: SRAM
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CPU Frequency 50322800 Hz
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CPU Frequency 50327388 Hz
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CPU HartID: 0
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-----Nuclei RISC-V CPU Configuration Information-----
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MARCHID: 0x900
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MIMPID: 0x30900
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ISA: RV64 A B C D F I M S U Zc Xxlcz
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MCFG: ECLIC PLIC ICACHE DCACHE SMP ZC_XLCZ_EXT IREGION No-Safety-Mechanism DLEN=VLEN/2
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ICACHE: 64 KB(set=512,way=2,lsize=64,ecc=0)
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DCACHE: 64 KB(set=512,way=2,lsize=64,ecc=0)
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TLB: MainTLB(set=256,way=4,entry=1,ecc=0) ITLB(entry=16) DTLB(entry=16)
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IREGION: 0x18000000 128 MB
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Unit Size Address
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INFO 64KB 0x18000000
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DEBUG 64KB 0x18010000
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ECLIC 64KB 0x18020000
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TIMER 64KB 0x18030000
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SMP 64KB 0x18040000
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CIDU 64KB 0x18050000
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PLIC 64MB 0x1c000000
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SMP_CFG: CC_PRESENT=1 SMP_NUM=8 IOCP_NUM=0 PMON_NUM=4
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ECLIC: VERSION=0x0 NUM_INTERRUPT=71 CLICINTCTLBITS=3 MTH=0 NLBITS=3
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L2CACHE: 2 MB(set=2048,way=16,lsize=64,ecc=0)
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INFO-Detail:
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mpasize : 32
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MARCHID: 0x1000
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MIMPID: 0x10300
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ISA: RV64 A B C D F H I M S U V
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MCFG: ECLIC PLIC ICACHE DCACHE SMP IREGION SSTC No-Safety-Mechanism DLEN=VLEN
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ICACHE: 128 KB(set=512,way=4,lsize=64,ecc=0)
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DCACHE: 128 KB(set=1024,way=2,lsize=64,ecc=0)
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TLB: MainTLB(entry=256,way=4,ecc=0) ITLB(entry=16) DTLB(entry=16)
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IREGION: 0x18000000 128 MB
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Unit Size Address
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INFO 64KB 0x18000000
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DEBUG 64KB 0x18010000
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ECLIC 64KB 0x18020000
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TIMER 64KB 0x18030000
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SMP 64KB 0x18040000
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PLIC 64MB 0x1c000000
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SMP_CFG: CC_PRESENT=1 SMP_NUM=1 IOCP_NUM=0 PMON_NUM=4
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ECLIC: VERSION=0x1 NUM_INTERRUPT=147 CLICINTCTLBITS=3 MTH=0 NLBITS=3
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L2CACHE: 2 MB(set=2048,way=16,lsize=64,ecc=0)
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INFO-Detail:
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mpasize : 35
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prefetch: present
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prefetch_mode: normal
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status: disable
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version=4
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l2_pf_lbuf_num=10
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l2_pf_dbuf_num=2
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l1d_ena=1
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cc_ena=1
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scalar_ena=1
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vector_ena=1
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write_pref_ena=1
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cross_page_pref_ena=1
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pref_conflict_stop_th=1
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pref_conflict_decr_sel=2
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degree_incr_th=0
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degree_decr_th=0
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next_line_ena_th=5
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write_noalloc_l1_th=0
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write_noalloc_l2_th=0
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max_stream_l1_degree=6
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max_stream_l2_degree=16
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max_stride_cplx_l1_degree=3
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max_stride_cplx_l2_degree=8
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isa supported: present
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extension_list: vector smepmp sscofpmf zfh zfa svnapot svpbmt svinval bf16 zimop zcmop zicond zihintntl zihintpause zihpm smcntrpmf zicntr zawrs
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vpu: present
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vpu_extension_list: vector_b zve64f zve64d zvfh
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noseg_noshuf=0
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elen64=1
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vlm: absent
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flash bus: absent
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mem_region0: absent
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mem_region1: absent
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cppi: absent
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cmo: present
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cbozero_size: 64 Bytes
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cmo_size: 64 Bytes
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cmo_prefetch=1
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hw performance: present
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bus: ICB
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fpu_cycle=5
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high_div=1
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dcache_2stage=1
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delay_branch_flush=0
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dual_issue=0
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cross_4k=0
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dlm_2stage=0
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lsu_cut_fwd=0
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dsp_cycle=0
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ifu_cut_timing=0
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mem_cut_timing=0
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dcache_prefetch=0
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dcache_lbuf_num=4
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mul_cyc=3
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vfpu_cyc=4
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bht_entry_width=2
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high_performance=1
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agu_quick_forward=1
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cau_fwd=0
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hpm_ver=2
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misc:
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ws_tmout_max=767
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nc_tmout_max=0
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dev_store_early_ret=0
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pf_access=0
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cache_csr_access=0
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pma_csr_access=0
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-----End of Nuclei CPU INFO-----
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.. _design_app_demo_timer:

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