fpga_diff: expose extra IO with difftest createTopIOs

Author: klin02

src/main/scala/sim/NutShellSim.scala

@@ -45,7 +45,8 @@ class NutShellSim extends Module with HasDiffTestInterfaces {
 
   val uart = IO(new UARTIO)
   uart <> mmio.io.uart
-  override def connectTopIOs(difftest: DifftestTopIO): Unit = {
+  override def connectTopIOs(difftest: DifftestTopIO): Seq[Data] = {
     difftest.uart <> uart
+    Seq.empty
   }
 }

src/test/scala/TopMain.scala

@@ -39,9 +39,8 @@ class Top extends Module {
 class FpgaDiffTop extends NutShell()(NutCoreConfig(FPGADifftest = true)) with HasDiffTestInterfaces {
   override def desiredName: String = "NutShell"
   override def cpuName: Option[String] = Some("NutShell")
-  override def connectTopIOs(difftest: DifftestTopIO): Unit = {
-    val io = IO(chiselTypeOf(this.io))
-    io <> this.io
+  override def connectTopIOs(difftest: DifftestTopIO): Seq[Data] = {
+    Seq(io)
   }
 }