Bump Chisel 7.0.0 (#235)

Author: poemonsense

build.sc

@@ -3,8 +3,8 @@ import coursier.maven.MavenRepository
 
 object ivys {
   val scala = "2.13.14"
-  val chisel = ivy"org.chipsalliance::chisel:6.7.0"
-  val chiselPlugin = ivy"org.chipsalliance:::chisel-plugin:6.7.0"
+  val chisel = ivy"org.chipsalliance::chisel:7.0.0"
+  val chiselPlugin = ivy"org.chipsalliance:::chisel-plugin:7.0.0"
 }
 
 trait CommonModule extends ScalaModule {

difftest

@@ -78,7 +78,8 @@ class NutShell(implicit val p: NutCoreConfig) extends Module with HasSoCParamete
       l2cacheIn
     } else xbar.io.out
     val l2Empty = Wire(Bool())
-    l2cacheOut <> Cache(in = l2cacheIn, mmio = 0.U.asTypeOf(new SimpleBusUC) :: Nil, flush = "b00".U, empty = l2Empty, enable = true)(
+    val mmio = WireInit(0.U.asTypeOf(new SimpleBusUC))
+    l2cacheOut <> Cache(in = l2cacheIn, mmio = mmio :: Nil, flush = "b00".U, empty = l2Empty, enable = true)(
       CacheConfig(name = "l2cache", totalSize = 128, cacheLevel = 2))
     l2cacheOut.coh.resp.ready := true.B
     l2cacheOut.coh.req.valid := false.B