fpga_diff: fix FpgaDiffTop generation and renaming

This change generates FpgaDiffTop as extend instead of wrapper.

Also, when use `make verilog BOARD=fpgadiff`, the top sv file is
SimTop.sv rather than FpgaDiffTop.sv, this change also revert previous
naming error.

Author: klin02

src/test/scala/TopMain.scala

@@ -36,12 +36,8 @@ class Top extends Module {
   dontTouch(vga.io)
 }
 
-class FpgaDiffTop extends Module with HasDiffTestInterfaces {
-  lazy val config = NutCoreConfig(FPGADifftest = true)
-  val soc = Module(new NutShell()(config))
-  val io = IO(soc.io.cloneType)
-  soc.io <> io
-
+class FpgaDiffTop extends NutShell()(NutCoreConfig(FPGADifftest = true)) with HasDiffTestInterfaces {
+  override def desiredName: String = "NutShell"
   override def cpuName: Option[String] = Some("NutShell")
   override def connectTopIOs(difftest: DifftestTopIO): Unit = {
     val io = IO(chiselTypeOf(this.io))