Commit ecb79dd
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3 files changed
+2
-6
lines changed- src
- main/scala/sim
- test/scala
3 files changed
+2
-6
lines changed- .github/workflows/format.yml+1-1
- .github/workflows/fpga.yml+122
- .github/workflows/main.yml+89-10
- Makefile+4-1
- README.md+11-6
- config/config.h+1-5
- emu.mk+13-1
- fpga.mk+5-1
- galaxsim.mk+1-1
- gsim.mk+28-3
- libso.mk+1-1
- palladium.mk+1-1
- pdb.mk+2-2
- scripts/fpga/ci.py+511
- scripts/fpga/release.sh+140
- scripts/st_tools/interface.py+62-8
- src/main/scala/Bundles.scala+12-17
- src/main/scala/DPIC.scala+75-49
- src/main/scala/Delta.scala+108-18
- src/main/scala/Difftest.scala+91-91
- src/main/scala/Gateway.scala+18-14
- src/main/scala/Preprocess.scala+12-13
- src/main/scala/Replay.scala+1-1
- src/main/scala/SimTop.scala+35-6
- src/main/scala/Squash.scala+2-2
- src/main/scala/common/Mem.scala+2-1
- src/main/scala/util/Profile.scala+14-6
- src/main/scala/util/Query.scala+5-2
- src/test/csrc/common/args.cpp+308
- src/test/csrc/common/args.h+74
- src/test/csrc/common/common.h+12
- src/test/csrc/common/compress.cpp+4-3
- src/test/csrc/common/dut.h-12
- src/test/csrc/common/golden.cpp+1-1
- src/test/csrc/common/golden.h+3-17
- src/test/csrc/common/mpool.h-1
- src/test/csrc/common/ram.cpp+1-1
- src/test/csrc/difftest/checkers.h+403
- src/test/csrc/difftest/checkers/globalmem.cpp+239
- src/test/csrc/difftest/checkers/instructions.cpp+170
- src/test/csrc/difftest/checkers/load.cpp+257
- src/test/csrc/difftest/checkers/refill.cpp+131
- src/test/csrc/difftest/checkers/store.cpp+67
- src/test/csrc/difftest/checkers/sync_states.cpp+110
- src/test/csrc/difftest/checkers/tlb.cpp+237
- src/test/csrc/difftest/checkers/traps.cpp+152
- src/test/csrc/difftest/diffstate.cpp+90
- src/test/csrc/difftest/diffstate.h+199
- src/test/csrc/difftest/difftest.cpp+203-1.3k
- src/test/csrc/difftest/difftest.h+52-316
- src/test/csrc/difftest/refproxy.cpp+39-38
- src/test/csrc/difftest/refproxy.h+33-44
- src/test/csrc/emu/emu.cpp+19-319
- src/test/csrc/emu/emu.h+3-52
- src/test/csrc/fpga/fpga_main.cpp+42-65
- src/test/csrc/fpga/xdma.h-1
- src/test/csrc/plugin/runahead/runahead.cpp+4-4
- src/test/csrc/plugin/xspdb/cpp/export.cpp-4
- src/test/csrc/plugin/xspdb/cpp/export.h-1
- src/test/csrc/plugin/xspdb/swig.i+16-3
- src/test/csrc/vcs/vcs_main.cpp+74-55
- src/test/scala/DifftestMain.scala+1
- src/test/scala/DifftestTop.scala+37-37
- src/test/vsrc/fpga_sim/xdma_axi.v+1-1
- src/test/vsrc/fpga_sim/xdma_wrapper.v+1-1
- src/test/vsrc/vcs/DeferredControl.v+1-1
- src/test/vsrc/vcs/DifftestEndpoint.sv+13-4
- src/test/vsrc/vcs/top.v+1-1
- vcs.mk+1-1
- verilator.mk+29-2
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