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Description
For verification components, common enumeration types should be upstreamed from specific VCs like SPI to the common package, so multiple VCs can reuse these types.
Proposed Additions
1. Common Enumeration Types:
type ClockPolarity is (HIGH_ACTIVE, LOW_ACTIVE);
type ClockPhase is (RISING_EDGE, FALLING_EDGE);
type BitOrder is (LSB_FIRST, MSB_FIRST);2. Overloaded Operators:
function "xor" (Left : std_logic; Right: SpiClockPolarity) return std_logic;Bodies:
function "xor" (Left : std_logic; Right: SpiClockPolarity) return std_logic is
begin
if Right = LOW_ACTIVE then
return not Left;
else
return Left;
end if;
end function; 3. Helper Functions and Converters:
function position(iterator: natural; length: natural; bitOrder : SpiBitOrder) return natural;
function to_sl(ClockPhase : SpiClockPhase) return std_logic;
function to_sl(ClockPolarity : SpiClockPolarity) return std_logic;Bodies:
function position(iterator: natural; length: natural; bitOrder : SpiBitOrder) return natural is
begin
if bitOrder = LSB_FIRST then
return iterator; -- filling from left to right in a downto vector
else
return length - iterator - 1; -- filling from right to left in a downto vector
end if;
end function;
function to_sl(ClockPhase : SpiClockPhase) return std_logic is
begin
if ClockPhase = FALLING_EDGE then
return '0';
else
return '1';
end if;
end function;
function to_sl(ClockPolarity : SpiClockPolarity) return std_logic is
begin
if ClockPolarity = LOW_ACTIVE then
return '0';
else
return '1';
end if;
end function;Usecases
XOR Operator
SCLK <= SpiClock xor ClockPolarity;Position Function
MOSI <= TransmitStim.Data(position(i, TransmitStim.Data'length, BitOrder)) after tpd_Clk_MOSI;to_sl(..) Conversion
wait until SCLK = to_sl(ClockPhase);Further Improvements
If OSVVM has a boolean to std_ulogic conversion, then some of the if..else-statements could be replaced by a function call.
/cc @Asif71
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