Updated doc

Author: JimLewis

Overview/Osvvm1About.rst

@@ -9,30 +9,31 @@ About OSVVM
 About OSVVM
 ====================================================
 
-OSVVM is an advanced verification methodology that
+OSVVM is an advanced verification methodology that 
 defines a VHDL verification framework, verification utility library, 
 verification component library, scripting API, and co-simulation capability 
 that simplifies your FPGA or ASIC verification project from start to finish. 
 Using these libraries you can create a simple, readable, 
-and powerful testbench that is suitable for either a 
-simple FPGA block or a complex ASIC.  
+and powerful testbench that will boost productivity for either 
+low level block tests (unit tests) or complex FPGA and ASIC tests.
 
 OSVVM is developed by the same VHDL experts who
 have helped develop VHDL standards.
 We have used our expert VHDL skills to create
 advanced verification capabilities that provide:  
 
-- A structured transaction-based verification framework using verification components.  
-- A common, shared transaction API for address bus (AXI4, Axi4Lite, Avalon, …) and streaming (AXI Stream, UART) verification components.    
-- Improved readability and reviewability by the whole team including software and system engineers.   
-- Improved reuse and reduced project schedules.    
-- Buzz word features including Constrained Random, Functional Coverage, Scoreboards, FIFOs, Memory Models, error logging and reporting, and message filtering that are simple to use and work like built-in language features.    
-- A common scripting API to run all simulators.  OSVVM scripting supports GHDL, NVC, Aldec Riviera-PRO and ActiveHDL, Siemens Questa and ModelSim, Synopsys VCS, and Cadence Xcelium.  
+- A structured transaction-based framework using verification components that is suitable for all verification tasks - from Unit/RTL to full chip/system level testing.
+- Test cases and verification components that can be written any VHDL Engineer.
+- Test cases that are readable and reviewable by the whole team including software and system engineers.   
+- Unmatched reuse through the entire verification process.    
 - Unmatched test reporting with HTML based test suite reports, test case reports, and logs that facilitate debug and test artifact collection.   
 - Support for continuous integration (CI/CD) with JUnit XML test suite reporting.  
+- Powerful and concise verification capabilities including Constrained Random, Functional Coverage, Scoreboards, FIFOs, Memory Models, error logging and reporting, and message filtering that are simple to use and work like built-in language features.
+- A common scripting API to run all simulators - including GHDL, NVC, Aldec Riviera-PRO and ActiveHDL, Siemens Questa and ModelSim, Synopsys VCS, and Cadence Xcelium.  
+- A Co-simulation capability that supports running software (C++) in a hardware simulation environment.
+- A Model Independent Transaction (MIT) library that defines a transaction API (procedures such as read, write, send, get, …)  and transaction interface (a record) that simplifies writing verification components and test cases.
 - A rival to the verification capabilities of SystemVerilog + UVM.  
 
-
 Looking to improve your VHDL verification methodology? 
 OSVVM provides a complete solution for VHDL ASIC or FPGA verification. 
 There is no new language to learn. 
@@ -77,7 +78,15 @@ Important benefits of OSVVM:
 * One Script to Run Simulators
     * Same script supports GHDL, Aldec Riviera-PRO and ActiveHDL, Siemens QuestaSim and ModelSim, Synopsys VCS, and Cadence Xcelium
 
-* It is free open source.
+* Co-simulation 
+    * Supports running software (C++) in a hardware simulation environment
+    * Write test cases in C++
+    * Run C++ models such as instruction set simulators
+
+* Tests and verification components can be written by any VHDL Engineer
+    * While on a project it is good to separate design and verification, our engineering team members should be able to do either.
+
+* It is free open source
     * It upgrades an ordinary VHDL license with full featured verification capabilities.
 
 SynthWorks has been using OSVVM for 25+ years in our