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[cbuild-run] Add datapatch handling and refine algorithm filtering
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8 files changed

+145
-23
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8 files changed

+145
-23
lines changed

‎test/packs/ARM/RteTest_DFP/0.2.0/ARM.RteTest_DFP.pdsc‎

Lines changed: 11 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -29,6 +29,8 @@
2929
RteTest ARM M Device Family
3030
</description>
3131
<algorithm name="Device/ARM/Flash/FAMILY.FLM" start="0x00000000" size="0x00040000" default="1"/>
32+
<algorithm name="Device/ARM/Flash/NonDefaultAlgo.FLM" start="0x00000000" size="0x00010000"/>
33+
<algorithm name="Device/ARM/Flash/IARAlgo.FLM" start="0x00000000" size="0x00020000" default="1" style="IAR"/>
3234
<debugvars configfile="Device/ARM/Debug/ARMCM.dbgconf" version="0.0.2">
3335
__var DbgMCU_CR = 0x00000007; // DBGMCU_CR: DBG_SLEEP, DBG_STOP, DBG_STANDBY
3436
__var TraceClk_Pin = 0x00040002; // PE2
@@ -138,8 +140,11 @@
138140
<debugport __dp="0"/>
139141
<debugport __dp="1"/>
140142
<debug defaultResetSequence="ResetSystem0" Pname="cm0_core0" __dp="0" __ap="0"/>
141-
<debug defaultResetSequence="ResetSystem1" Pname="cm0_core1" __dp="1" __ap="0"/>
142-
<algorithm name="Device/ARM/Flash/CortexM4Dual.FLM" start="0x000A0000" size="0x00020000" RAMstart="0x000C0000" RAMsize="0x00040000" Pname="cm0_core1"/>
143+
<debug defaultResetSequence="ResetSystem1" Pname="cm0_core1" __dp="1" __ap="0">
144+
<datapatch __dp="0" address="0xE0040FCC" value="0x11" info="DEVTYPE"/>
145+
<datapatch __dp="0" __ap="0" address="0xE0040FF0" value="0x0D" info="CIDR0"/>
146+
</debug>
147+
<algorithm name="Device/ARM/Flash/CortexM4Dual.FLM" start="0x000A0000" size="0x00020000" RAMstart="0x000C0000" RAMsize="0x00040000" Pname="cm0_core1" default="1"/>
143148
</device>
144149
<device Dname="RteTest_ARMCM0_Single">
145150
<processor Pname="cm0_core1" Dcore="Cortex-M0" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="NO_MPU" Dendian="Configurable" Dclock="10000000"/>
@@ -157,7 +162,9 @@
157162
<description>
158163
RteTest ARM Cortex M3 is a clone description from ARM.CMSIS pack.
159164
</description>
160-
<debug svd="Device/ARM/SVD/ARMCM3.svd"/> <!-- SVD files do not contain any peripheral -->
165+
<debug svd="Device/ARM/SVD/ARMCM3.svd"> <!-- SVD files do not contain any peripheral -->
166+
<datapatch __apid="4" address="0xE0040FF4" value="0x90" mask="0xFF" info="CIDR1"/>
167+
</debug>
161168
<accessportV1 __apid="2" index="20" HPROT="0x2" SPROT="1"/>
162169
<accessportV2 __apid="4" address="0x00400000" HPROT="0xF" SPROT="0"/>
163170

@@ -204,7 +211,7 @@
204211

205212
<variant Dvariant="RteTest_ARMCM4_NOFP">
206213
<processor Dfpu="NO_FPU"/>
207-
<algorithm name="Device/ARM/Flash/CortexM4Device.FLM" start="0x00000000" size="0x00020000" default="0"/>
214+
<algorithm name="Device/ARM/Flash/CortexM4Device.FLM" start="0x00000000" size="0x00020000" default="1"/>
208215
</variant>
209216

210217
<variant Dvariant="RteTest_ARMCM4_FP">

‎tools/projmgr/include/ProjMgrRunDebug.h‎

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -119,6 +119,18 @@ struct ProcessorType {
119119
std::string resetSequence;
120120
};
121121

122+
/**
123+
* @brief datapatch type
124+
*/
125+
struct DatapatchType {
126+
unsigned int apid;
127+
unsigned long long address;
128+
unsigned long long value;
129+
std::optional<unsigned long long> mask;
130+
std::string type;
131+
std::string info;
132+
};
133+
122134
/**
123135
* @brief access port type
124136
*/
@@ -128,6 +140,7 @@ struct AccessPortType {
128140
std::optional<unsigned long long> address;
129141
std::optional<unsigned int> hprot;
130142
std::optional<unsigned int> sprot;
143+
std::vector<DatapatchType> datapatch;
131144
std::vector<AccessPortType> accessPorts;
132145
};
133146

‎tools/projmgr/include/ProjMgrYamlParser.h‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -76,6 +76,7 @@ static constexpr const char* YAML_COPY_TO = "copy-to";
7676
static constexpr const char* YAML_CORE = "core";
7777
static constexpr const char* YAML_CREATED_BY = "created-by";
7878
static constexpr const char* YAML_CREATED_FOR = "created-for";
79+
static constexpr const char* YAML_DATAPATCH = "datapatch";
7980
static constexpr const char* YAML_DEBUG = "debug";
8081
static constexpr const char* YAML_DEBUG_SEQUENCES = "debug-sequences";
8182
static constexpr const char* YAML_DEBUG_VARS = "debug-vars";
@@ -139,6 +140,7 @@ static constexpr const char* YAML_LICENSES = "licenses";
139140
static constexpr const char* YAML_LICENSE_AGREEMENT = "license-agreement";
140141
static constexpr const char* YAML_LINKER = "linker";
141142
static constexpr const char* YAML_MAP = "map";
143+
static constexpr const char* YAML_MASK = "mask";
142144
static constexpr const char* YAML_MEMORY = "memory";
143145
static constexpr const char* YAML_MESSAGES = "messages";
144146
static constexpr const char* YAML_MISC = "misc";
@@ -223,6 +225,7 @@ static constexpr const char* YAML_UNDEFINE = "undefine";
223225
static constexpr const char* YAML_UPDATE = "update";
224226
static constexpr const char* YAML_VARIABLES = "variables";
225227
static constexpr const char* YAML_VARS = "vars";
228+
static constexpr const char* YAML_VALUE = "value";
226229
static constexpr const char* YAML_VERSION = "version";
227230
static constexpr const char* YAML_WARNINGS = "warnings";
228231
static constexpr const char* YAML_WHILE = "while";

‎tools/projmgr/schemas/common.schema.json‎

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2212,11 +2212,30 @@
22122212
"address": { "type": "number", "description": "The address to select this access port (APv2) in its parent's address space for a target access." },
22132213
"HPROT": { "type": "number", "description": "Value for HPROT (AHB Protection Control) bits." },
22142214
"SPROT": { "type": "number", "description": "Value for SPROT (Secure Protection Control) bit." },
2215+
"datapatch": { "$ref": "#/definitions/DatapatchesType" },
22152216
"accessports": { "$ref": "#/definitions/AccessPortsType" }
22162217
},
22172218
"additionalProperties": false,
22182219
"required": ["apid"]
22192220
},
2221+
"DatapatchesType": {
2222+
"description": "List of patch values a debugger shall apply when reading from the device.",
2223+
"type": "array",
2224+
"uniqueItems": true,
2225+
"items": { "$ref": "#/definitions/DatapatchType" }
2226+
},
2227+
"DatapatchType": {
2228+
"type": "object",
2229+
"properties": {
2230+
"address": { "type": "number", "description": "Address for which to apply the patch." },
2231+
"value": { "type": "number", "description": "Value to overwrite from device (for example in a ROM table)." },
2232+
"mask": { "type": "number", "description": "The bits to patch. Default: complete value is replaced." },
2233+
"type": { "type": "string", "description": "Type of data access to patch. Default is Mem." },
2234+
"info": { "type": "string", "description": "Descriptive text for diagnostics messages." }
2235+
},
2236+
"additionalProperties": false,
2237+
"required": ["address", "value"]
2238+
},
22202239
"DebugProcessorsType": {
22212240
"description": "Map of pname identifiers to access port IDs (mandatory for multi-processor devices).",
22222241
"type": "array",

‎tools/projmgr/src/ProjMgrCbuildRun.cpp‎

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -30,6 +30,7 @@ class ProjMgrCbuildRun : public ProjMgrCbuildBase {
3030
void SetProcessorsNode(YAML::Node node, const std::vector<ProcessorType>& processors);
3131
void SetDebugPortsNode(YAML::Node node, const std::vector<DebugPortType>& debugPorts);
3232
void SetAccessPortsNode(YAML::Node node, const std::vector<AccessPortType>& accessPorts);
33+
void SetDatapatchNode(YAML::Node node, const std::vector<DatapatchType>& datapatch);
3334
};
3435

3536
ProjMgrCbuildRun::ProjMgrCbuildRun(YAML::Node node,
@@ -189,11 +190,26 @@ void ProjMgrCbuildRun::SetAccessPortsNode(YAML::Node node, const vector<AccessPo
189190
if (ap.sprot.has_value()) {
190191
SetNodeValue(apNode[YAML_SPROT], ProjMgrUtils::ULLToHex(ap.sprot.value(), 1));
191192
}
193+
SetDatapatchNode(apNode[YAML_DATAPATCH], ap.datapatch);
192194
SetAccessPortsNode(apNode[YAML_ACCESSPORTS], ap.accessPorts);
193195
node.push_back(apNode);
194196
}
195197
}
196198

199+
void ProjMgrCbuildRun::SetDatapatchNode(YAML::Node node, const vector<DatapatchType>& datapatch) {
200+
for (const auto& patch : datapatch) {
201+
YAML::Node patchNode;
202+
SetNodeValue(patchNode[YAML_ADDRESS], ProjMgrUtils::ULLToHex(patch.address));
203+
SetNodeValue(patchNode[YAML_VALUE], ProjMgrUtils::ULLToHex(patch.value));
204+
if (patch.mask.has_value()) {
205+
SetNodeValue(patchNode[YAML_MASK], ProjMgrUtils::ULLToHex(patch.mask.value()));
206+
}
207+
SetNodeValue(patchNode[YAML_TYPE], patch.type);
208+
SetNodeValue(patchNode[YAML_INFO], patch.info);
209+
node.push_back(patchNode);
210+
}
211+
}
212+
197213
void ProjMgrCbuildRun::SetProcessorsNode(YAML::Node node, const vector<ProcessorType>& processors) {
198214
for (const auto& processor : processors) {
199215
if (processor.pname.empty() && processor.resetSequence.empty() && !processor.apid.has_value()) {

‎tools/projmgr/src/ProjMgrRunDebug.cpp‎

Lines changed: 71 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -136,6 +136,15 @@ bool ProjMgrRunDebug::CollectSettings(const vector<ContextItem*>& contexts) {
136136

137137
// set device/board programming algorithms
138138
for (const auto& [algorithm, _] : algorithms) {
139+
if (!algorithm->GetAttributeAsBool("default")) {
140+
continue;
141+
}
142+
if (algorithm->HasAttribute("style")) {
143+
const auto& style = algorithm->GetAttribute("style");
144+
if (style != "Keil" && style != "CMSIS") {
145+
continue;
146+
}
147+
}
139148
AlgorithmType item;
140149
item.algorithm = algorithm->GetOriginalAbsolutePath();
141150
item.start = algorithm->GetAttributeAsULL("start");
@@ -316,43 +325,85 @@ bool ProjMgrRunDebug::CollectSettings(const vector<ContextItem*>& contexts) {
316325
// debug and access ports collections
317326
map<unsigned int, vector<AccessPortType>> accessPortsMap;
318327
map<unsigned int, vector<AccessPortType>> accessPortsChildrenMap;
328+
map<unsigned int, vector<DatapatchType>> datapatchById;
329+
map<unsigned int, map<unsigned int, vector<DatapatchType>>> datapatchByIndex;
319330
const auto& accessPortsV1 = context0->rteDevice->GetEffectiveProperties("accessportV1", context0->deviceItem.pname);
320331
const auto& accessPortsV2 = context0->rteDevice->GetEffectiveProperties("accessportV2", context0->deviceItem.pname);
321332
const auto& debugPorts = context0->rteDevice->GetEffectiveProperties("debugport", context0->deviceItem.pname);
322333
const auto& defaultDp = debugPorts.empty() ? 0 : debugPorts.front()->GetAttributeAsInt("__dp");
323-
unsigned int uniqueApId = 0;
324334

325-
// iterate over pnames
326-
for (const auto& [pname, _] : pnames) {
327-
ProcessorType processor;
328-
processor.pname = pname;
329-
const auto& debug = context0->rteDevice->GetSingleEffectiveProperty("debug", pname);
330-
if (debug) {
331-
if (debug->HasAttribute("__apid")) {
332-
processor.apid = debug->GetAttributeAsInt("__apid");
335+
// datapatches
336+
for (const auto& [debug, _] : debugs) {
337+
Collection<RteItem*> datapatches;
338+
debug->GetChildrenByTag("datapatch", datapatches);
339+
for (const auto& datapatch : datapatches) {
340+
DatapatchType patch;
341+
patch.address = datapatch->GetAttributeAsULL("address");
342+
patch.value = datapatch->GetAttributeAsULL("value");
343+
if (datapatch->HasAttribute("mask")) {
344+
patch.mask = datapatch->GetAttributeAsULL("mask");
345+
}
346+
patch.type = datapatch->GetAttribute("type");
347+
patch.info = datapatch->GetAttribute("info");
348+
if (datapatch->HasAttribute("__apid")) {
349+
datapatchById[datapatch->GetAttributeAsInt("__apid")].push_back(patch);
350+
} else {
351+
const auto& dp = datapatch->GetAttributeAsInt("__dp", defaultDp);
352+
const auto& apIndex = datapatch->GetAttributeAsInt("__ap", debug->GetAttributeAsInt("__ap", 0));
353+
datapatchByIndex[dp][apIndex].push_back(patch);
333354
}
334-
// access ports from 'debug' property with non-default attributes
335-
if ((accessPortsV1.empty() && accessPortsV2.empty()) &&
336-
(!debug->GetProcessorName().empty() || debug->HasAttribute("__dp") || debug->HasAttribute("__ap"))) {
355+
}
356+
}
357+
// access ports from 'debug' property (legacy support)
358+
map<string, unsigned int> processorApMap;
359+
if (accessPortsV1.empty() && accessPortsV2.empty()) {
360+
unsigned int uniqueApId = 0;
361+
for (const auto& [debug, scope] : debugs) {
362+
if (scope.size() == 1) {
363+
const auto& pname = scope.front();
364+
if (pname.empty() && datapatchByIndex.empty() && !debug->HasAttribute("__dp") && !debug->HasAttribute("__ap")) {
365+
// unnamed core with default attributes, skip further access port discovering
366+
break;
367+
}
337368
// use a sequential unique ap id
338-
processor.apid = uniqueApId++;
339-
// add ap to access port map
369+
const auto& apid = uniqueApId++;
370+
// add ap node to access port map
340371
AccessPortType ap;
341-
auto dp = debug->GetAttributeAsInt("__dp", defaultDp);
372+
const auto& dp = debug->GetAttributeAsInt("__dp", defaultDp);
342373
ap.index = debug->GetAttributeAsInt("__ap", 0);
343-
ap.apid = processor.apid.value();
374+
ap.apid = apid;
375+
ap.datapatch = datapatchByIndex[dp][ap.index.value()];
344376
accessPortsMap[dp].push_back(ap);
377+
// add apid to processor map
378+
processorApMap[pname] = apid;
345379
}
346-
processor.resetSequence = debug->GetAttribute("defaultResetSequence");
347-
// 'punits': placeholder for future expansion
348-
processor.punits.clear();
349380
}
381+
}
382+
// processors
383+
for (const auto& [pname, _] : pnames) {
384+
ProcessorType processor;
385+
processor.pname = pname;
386+
for (const auto& [debug, scope] : debugs) {
387+
if (scope.size() == 1 && scope.front() == pname) {
388+
if (debug->HasAttribute("__apid")) {
389+
processor.apid = debug->GetAttributeAsInt("__apid");
390+
}
391+
processor.resetSequence = debug->GetAttribute("defaultResetSequence");
392+
}
393+
}
394+
// legacy apid
395+
if (!processor.apid.has_value() && processorApMap.find(pname) != processorApMap.end()) {
396+
processor.apid = processorApMap.at(pname);
397+
}
398+
// 'punits': placeholder for future expansion
399+
processor.punits.clear();
350400
m_runDebug.debugTopology.processors.push_back(processor);
351401
}
352402
// APv1
353403
for (const auto& accessPortV1 : accessPortsV1) {
354404
AccessPortType ap;
355405
ap.apid = accessPortV1->GetAttributeAsInt("__apid");
406+
ap.datapatch = datapatchById[ap.apid];
356407
if (accessPortV1->HasAttribute("index")) {
357408
ap.index = accessPortV1->GetAttributeAsInt("index");
358409
}
@@ -364,6 +415,7 @@ bool ProjMgrRunDebug::CollectSettings(const vector<ContextItem*>& contexts) {
364415
for (const auto& accessPortV2 : accessPortsV2) {
365416
AccessPortType ap;
366417
ap.apid = accessPortV2->GetAttributeAsInt("__apid");
418+
ap.datapatch = datapatchById[ap.apid];
367419
if (accessPortV2->HasAttribute("address")) {
368420
ap.address = accessPortV2->GetAttributeAsULL("address");
369421
}

‎tools/projmgr/test/data/TestRunDebug/ref/run-debug+TestHW2.cbuild-run.yml‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -132,3 +132,8 @@ cbuild-run:
132132
address: 0x00400000
133133
HPROT: 0xF
134134
SPROT: 0x0
135+
datapatch:
136+
- address: 0xE0040FF4
137+
value: 0x00000090
138+
mask: 0x000000FF
139+
info: CIDR1

‎tools/projmgr/test/data/TestRunDebug/ref/run-debug+TestHW3.cbuild-run.yml‎

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -133,6 +133,13 @@ cbuild-run:
133133
accessports:
134134
- apid: 0
135135
index: 0
136+
datapatch:
137+
- address: 0xE0040FCC
138+
value: 0x00000011
139+
info: DEVTYPE
140+
- address: 0xE0040FF0
141+
value: 0x0000000D
142+
info: CIDR0
136143
- dpid: 1
137144
accessports:
138145
- apid: 1

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