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brondanibrondani
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[cbuild-run] debug-topology refinements
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4 files changed

+57
-27
lines changed

4 files changed

+57
-27
lines changed

‎test/packs/ARM/RteTest_DFP/0.2.0/ARM.RteTest_DFP.pdsc‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -135,8 +135,10 @@
135135
<compile header="Device/ARM/ARMCM0/Include/ARMCM0.h" define="ARMCM0"/>
136136
<memory name="FLASH_DUAL" access="rx" start="0x00000000" size="0x00080000" startup="1" default="1" Pname="cm0_core0"/>
137137
<memory name="SRAM_DUAL" access="rwx" start="0x80000000" size="0x00020000" uninit="1" default="1" Pname="cm0_core1"/>
138-
<debug defaultResetSequence="ResetSystem0" Pname="cm0_core0"/>
139-
<debug defaultResetSequence="ResetSystem1" Pname="cm0_core1"/>
138+
<debugport __dp="0"/>
139+
<debugport __dp="1"/>
140+
<debug defaultResetSequence="ResetSystem0" Pname="cm0_core0" __dp="0" __ap="0"/>
141+
<debug defaultResetSequence="ResetSystem1" Pname="cm0_core1" __dp="1" __ap="0"/>
140142
<algorithm name="Device/ARM/Flash/CortexM4Dual.FLM" start="0x000A0000" size="0x00020000" RAMstart="0x000C0000" RAMsize="0x00040000" Pname="cm0_core1"/>
141143
</device>
142144
<device Dname="RteTest_ARMCM0_Single">

‎tools/projmgr/schemas/common.schema.json‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2231,8 +2231,7 @@
22312231
"apid": { "type": "number", "description": "Access port ID to use for this processor." },
22322232
"reset-sequence": { "type": "string", "description": "Name of debug sequence for reset operation" }
22332233
},
2234-
"additionalProperties": false,
2235-
"required": ["pname"]
2234+
"additionalProperties": false
22362235
},
22372236
"DebugPunitsType": {
22382237
"description": "Specifies processor units in a symmetric multi-processor core (MPCore).",

‎tools/projmgr/src/ProjMgrRunDebug.cpp‎

Lines changed: 39 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -56,33 +56,30 @@ bool ProjMgrRunDebug::CollectSettings(const vector<ContextItem*>& contexts) {
5656
// debug sequences
5757
vector<pair<const RteItem*, vector<string>>> debugSequences;
5858

59-
// processor names
60-
map<string, ContextItem*> pnames;
61-
for (const auto& context : contexts) {
62-
pnames.emplace(context->deviceItem.pname, context);
63-
}
59+
// all processors
60+
const auto& pnames = context0->rteDevice->GetProcessors();
6461

6562
// device collections
66-
for (const auto& [pname, context] : pnames) {
67-
if (context->devicePack) {
68-
m_runDebug.devicePack = context->devicePack->GetPackageID(true);
69-
const auto& deviceAlgorithms = context->rteDevice->GetEffectiveProperties("algorithm", pname);
63+
for (const auto& [pname, _] : pnames) {
64+
if (context0->devicePack) {
65+
m_runDebug.devicePack = context0->devicePack->GetPackageID(true);
66+
const auto& deviceAlgorithms = context0->rteDevice->GetEffectiveProperties("algorithm", pname);
7067
for (const auto& deviceAlgorithm : deviceAlgorithms) {
7168
PushBackUniquely(algorithms, deviceAlgorithm, pname);
7269
}
73-
const auto& deviceMemories = context->rteDevice->GetEffectiveProperties("memory", pname);
70+
const auto& deviceMemories = context0->rteDevice->GetEffectiveProperties("memory", pname);
7471
for (const auto& deviceMemory : deviceMemories) {
7572
PushBackUniquely(memories, deviceMemory, pname);
7673
}
77-
const auto& deviceDebugs = context->rteDevice->GetEffectiveProperties("debug", pname);
74+
const auto& deviceDebugs = context0->rteDevice->GetEffectiveProperties("debug", pname);
7875
for (const auto& deviceDebug : deviceDebugs) {
7976
PushBackUniquely(debugs, deviceDebug, pname);
8077
}
81-
const auto& deviceDebugVars = context->rteDevice->GetEffectiveProperties("debugvars", pname);
78+
const auto& deviceDebugVars = context0->rteDevice->GetEffectiveProperties("debugvars", pname);
8279
for (const auto& deviceDebugVar : deviceDebugVars) {
8380
PushBackUniquely(debugvars, deviceDebugVar, pname);
8481
}
85-
const auto& deviceDebugSequences = context->rteDevice->GetEffectiveProperties("sequence", pname);
82+
const auto& deviceDebugSequences = context0->rteDevice->GetEffectiveProperties("sequence", pname);
8683
for (const auto& deviceDebugSequence : deviceDebugSequences) {
8784
PushBackUniquely(debugSequences, deviceDebugSequence, pname);
8885
}
@@ -315,28 +312,44 @@ bool ProjMgrRunDebug::CollectSettings(const vector<ContextItem*>& contexts) {
315312
m_runDebug.debugTopology.sdf = debugConfig->GetAbsolutePackagePath() + sdf;
316313
}
317314
}
318-
for (const auto& [pname, context] : pnames) {
315+
316+
// debug and access ports collections
317+
map<unsigned int, vector<AccessPortType>> accessPortsMap;
318+
map<unsigned int, vector<AccessPortType>> accessPortsChildrenMap;
319+
const auto& accessPortsV1 = context0->rteDevice->GetEffectiveProperties("accessportV1", context0->deviceItem.pname);
320+
const auto& accessPortsV2 = context0->rteDevice->GetEffectiveProperties("accessportV2", context0->deviceItem.pname);
321+
const auto& debugPorts = context0->rteDevice->GetEffectiveProperties("debugport", context0->deviceItem.pname);
322+
const auto& defaultDp = debugPorts.empty() ? 0 : debugPorts.front()->GetAttributeAsInt("__dp");
323+
unsigned int uniqueApId = 0;
324+
325+
// iterate over pnames
326+
for (const auto& [pname, _] : pnames) {
319327
ProcessorType processor;
320328
processor.pname = pname;
321-
const auto& debug = context->rteDevice->GetSingleEffectiveProperty("debug", pname);
329+
const auto& debug = context0->rteDevice->GetSingleEffectiveProperty("debug", pname);
322330
if (debug) {
323331
if (debug->HasAttribute("__apid")) {
324332
processor.apid = debug->GetAttributeAsInt("__apid");
325333
}
334+
// access ports from 'debug' property with non-default attributes
335+
if ((accessPortsV1.empty() && accessPortsV2.empty()) &&
336+
(!debug->GetProcessorName().empty() || debug->HasAttribute("__dp") || debug->HasAttribute("__ap"))) {
337+
// use a sequential unique ap id
338+
processor.apid = uniqueApId++;
339+
// add ap to access port map
340+
AccessPortType ap;
341+
auto dp = debug->GetAttributeAsInt("__dp", defaultDp);
342+
ap.index = debug->GetAttributeAsInt("__ap", 0);
343+
ap.apid = processor.apid.value();
344+
accessPortsMap[dp].push_back(ap);
345+
}
326346
processor.resetSequence = debug->GetAttribute("defaultResetSequence");
327347
// 'punits': placeholder for future expansion
328348
processor.punits.clear();
329349
}
330350
m_runDebug.debugTopology.processors.push_back(processor);
331351
}
332-
333-
map<unsigned int, vector<AccessPortType>> accessPortsMap;
334-
map<unsigned int, vector<AccessPortType>> accessPortsChildrenMap;
335-
const auto& accessPortsV1 = context0->rteDevice->GetEffectiveProperties("accessportV1", context0->deviceItem.pname);
336-
const auto& accessPortsV2 = context0->rteDevice->GetEffectiveProperties("accessportV2", context0->deviceItem.pname);
337-
const auto& debugPorts = context0->rteDevice->GetEffectiveProperties("debugport", context0->deviceItem.pname);
338-
const auto& defaultDp = debugPorts.empty() ? 0 : debugPorts.front()->GetAttributeAsInt("__dp");
339-
352+
// APv1
340353
for (const auto& accessPortV1 : accessPortsV1) {
341354
AccessPortType ap;
342355
ap.apid = accessPortV1->GetAttributeAsInt("__apid");
@@ -347,6 +360,7 @@ bool ProjMgrRunDebug::CollectSettings(const vector<ContextItem*>& contexts) {
347360
auto dp = accessPortV1->GetAttributeAsInt("__dp", defaultDp);
348361
accessPortsMap[dp].push_back(ap);
349362
}
363+
// APv2
350364
for (const auto& accessPortV2 : accessPortsV2) {
351365
AccessPortType ap;
352366
ap.apid = accessPortV2->GetAttributeAsInt("__apid");
@@ -362,6 +376,7 @@ bool ProjMgrRunDebug::CollectSettings(const vector<ContextItem*>& contexts) {
362376
accessPortsMap[dp].push_back(ap);
363377
}
364378
}
379+
// construct debug ports tree
365380
if (debugPorts.empty() && !accessPortsMap.empty()) {
366381
// default debug port
367382
m_runDebug.debugTopology.debugPorts.push_back({0});
@@ -418,6 +433,7 @@ FilesType ProjMgrRunDebug::SetLoadFromOutput(const ContextItem* context, OutputT
418433
load.file = output.filename;
419434
load.info = "generate by " + context->name;
420435
load.type = type;
436+
load.pname = context->deviceItem.pname;
421437
}
422438
return load;
423439
}

‎tools/projmgr/test/data/TestRunDebug/ref/run-debug+TestHW3.cbuild-run.yml‎

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -9,9 +9,11 @@ cbuild-run:
99
- file: out/core0/TestHW3/core0.axf
1010
info: generate by core0+TestHW3
1111
type: elf
12+
pname: cm0_core0
1213
- file: out/core1/TestHW3/core1.axf
1314
info: generate by core1+TestHW3
1415
type: elf
16+
pname: cm0_core1
1517
- file: ../data/TestRunDebug/customImage.bin
1618
info: load image info
1719
type: bin
@@ -126,8 +128,19 @@ cbuild-run:
126128
ram-start: 0x20000000
127129
ram-size: 0x00020000
128130
debug-topology:
131+
debugports:
132+
- dpid: 0
133+
accessports:
134+
- apid: 0
135+
index: 0
136+
- dpid: 1
137+
accessports:
138+
- apid: 1
139+
index: 0
129140
processors:
130141
- pname: cm0_core0
142+
apid: 0
131143
reset-sequence: ResetSystem0
132144
- pname: cm0_core1
145+
apid: 1
133146
reset-sequence: ResetSystem1

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