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Merge branch 'main' into dependabot/github_actions/step-security/harden-runner-2.11.1
2 parents 88931da + aacb0d4 commit f4d23f3

31 files changed

+801
-181
lines changed

libs/rtemodel/src/RteItem.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -781,7 +781,7 @@ bool RteItem::IsExecuteAccess()
781781
{
782782
const string& id = GetAttribute("id");
783783
if (!id.empty()) {
784-
return id.find("IROM") == 0;
784+
return id.find("IROM") == 0 || id.find("IRAM") == 0;
785785
}
786786
const string& access = GetAccess();
787787
return access.find('x') != string::npos;

libs/rtemodel/test/src/RteChkTest.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -30,9 +30,9 @@ Generic: 4\n\
3030
DFP: 3\n\
3131
BSP: 1\n\
3232
\n\
33-
Components: 59\n\
33+
Components: 60\n\
3434
From generic packs: 36\n\
35-
From DFP: 23\n\
35+
From DFP: 24\n\
3636
From BSP: 0\n\
3737
\n\
3838
Devices: 10\n\
@@ -51,7 +51,7 @@ completed\n";
5151
int res = rteChk.RunCheckRte();
5252
EXPECT_EQ(res, 0);
5353
EXPECT_EQ(rteChk.GetPackCount(), 8);
54-
EXPECT_EQ(rteChk.GetComponentCount(), 59);
54+
EXPECT_EQ(rteChk.GetComponentCount(), 60);
5555
EXPECT_EQ(rteChk.GetDeviceCount(), 10);
5656
EXPECT_EQ(rteChk.GetBoardCount(), 14);
5757

test/packs/ARM/RteTest_DFP/0.2.0/ARM.RteTest_DFP.pdsc

Lines changed: 26 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -133,6 +133,11 @@
133133
<processor Pname="cm0_core0" Dcore="Cortex-M0" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="NO_MPU" Dendian="Configurable" Dclock="10000000" />
134134
<processor Pname="cm0_core1" Dcore="Cortex-M0" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="NO_MPU" Dendian="Configurable" Dclock="10000000"/>
135135
<compile header="Device/ARM/ARMCM0/Include/ARMCM0.h" define="ARMCM0"/>
136+
<memory name="FLASH_DUAL" access="rx" start="0x00000000" size="0x00080000" startup="1" default="1" Pname="cm0_core0"/>
137+
<memory name="SRAM_DUAL" access="rwx" start="0x80000000" size="0x00020000" uninit="1" default="1" Pname="cm0_core1"/>
138+
<debug defaultResetSequence="ResetSystem0" Pname="cm0_core0"/>
139+
<debug defaultResetSequence="ResetSystem1" Pname="cm0_core1"/>
140+
<algorithm name="Device/ARM/Flash/CortexM4Dual.FLM" start="0x000A0000" size="0x00020000" RAMstart="0x000C0000" RAMsize="0x00040000" Pname="cm0_core1"/>
136141
</device>
137142
<device Dname="RteTest_ARMCM0_Single">
138143
<processor Pname="cm0_core1" Dcore="Cortex-M0" DcoreVersion="r0p0" Dfpu="NO_FPU" Dmpu="NO_MPU" Dendian="Configurable" Dclock="10000000"/>
@@ -151,6 +156,9 @@
151156
RteTest ARM Cortex M3 is a clone description from ARM.CMSIS pack.
152157
</description>
153158
<debug svd="Device/ARM/SVD/ARMCM3.svd"/> <!-- SVD files do not contain any peripheral -->
159+
<accessportV1 __apid="2" index="20" HPROT="0x2" SPROT="1"/>
160+
<accessportV2 __apid="4" address="0x00400000" HPROT="0xF" SPROT="0"/>
161+
154162
<memory id="IROM1" start="0x00000000" size="0x00040000" startup="1" default="1"/>
155163
<memory id="IRAM1" start="0x20000000" size="0x00020000" uninit="1" default="1"/>
156164

@@ -166,13 +174,23 @@
166174
<description>
167175
RteTest ARM Cortex M4 is a clone description from ARM.CMSIS pack.
168176
</description>
169-
<debugconfig default="jtag" clock="40000000"/>
177+
<debugconfig default="jtag" clock="40000000" swj="0" dormant="1" sdf="Device/ARM/Debug/ARMCM4.sdf"/>
178+
<debugport __dp="0">
179+
<jtag tapindex="7"/>
180+
</debugport>
181+
<debugport __dp="1">
182+
<swd targetsel="8"/>
183+
</debugport>
170184
<debugvars configfile="Device/ARM/Debug/ARMCM4.dbgconf" version="0.2.1" >
171185
__var DbgMCU_CR = 0x00000007; // DBGMCU_CR: DBG_SLEEP, DBG_STOP, DBG_STANDBY
172186
__var TraceClk_Pin = 0x00040003; // PE2
173187
__var TraceD0_Pin = 0x00040003; // PE4
174188
</debugvars>
175189
<debug svd="Device/ARM/SVD/ARMCM4.svd"/> <!-- SVD files do not contain any peripheral -->
190+
<accessportV1 __apid="1" index="10"/>
191+
<accessportV2 __apid="2" address="0x00200000"/>
192+
<accessportV2 __apid="3" address="0x00300000" parent="2"/>
193+
176194
<memory name="FLASH" access="rx" start="0x00000000" size="0x00040000" startup="1" default="1"/>
177195
<memory name="SRAM" access="rwx" start="0x20000000" size="0x00020000" uninit="1" default="1"/>
178196
<algorithm name="Device/ARM/Flash/CortexM4SubFamily.FLM" start="0x00000000" size="0x00040000" default="1"/>
@@ -435,6 +453,13 @@
435453
</files>
436454
</component>
437455

456+
<component Cclass="RteTest" Cgroup="scvd" Cversion="1.1.1" condition="ARMCM3 RteTest">
457+
<description>scvd test</description>
458+
<files>
459+
<file category="other" name="Components/RteTest.scvd"/>
460+
</files>
461+
</component>
462+
438463
</components>
439464

440465
<boards>
Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,2 @@
1+
// scvd
2+
Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1 @@
1+
// sdf
Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1 @@
1+
CortexM4Dual.FLM : not real flash algorithm

tools/packchk/src/ValidateSemantic.cpp

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -277,11 +277,13 @@ bool ValidateSemantic::CheckMemories(RteDeviceItem* device)
277277
}
278278
}
279279

280-
// Check startup attribute
280+
// Check startup attribute
281281
if(startup == "1") {
282282
rxRegionWithStartup.push_back(memory);
283-
if(access.find_first_of("x") == string::npos) {
284-
LogMsg("M608", NAME(memoryName), ATTR("startup"), VALUE("1"), ATTR2("access"), VALUE2("x"), lineNo);
283+
if(id.find("IROM") != 0 && id.find("IRAM") != 0) { // no deprecated IRAM / IROM which have eXecute implicitly set
284+
if(access.find_first_of("x") == string::npos) {
285+
LogMsg("M608", NAME(memoryName), ATTR("startup"), VALUE("1"), ATTR2("access"), VALUE2("x"), lineNo);
286+
}
285287
}
286288
}
287289
}

tools/packchk/test/data/MemoryAttributes/TestVendor.MemoryAttributes.pdsc

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -42,6 +42,15 @@
4242
The TestSubFamily is ...
4343
</description>
4444

45+
<!-- ************************* TestDeviceOk, old IDs ************************ -->
46+
<device Dname="TestDeviceOkOldIDs">
47+
<processor Dcore="Cortex-M4" DcoreVersion="r0p1" Dfpu="SP_FPU" Dmpu="MPU" Ddsp="NO_DSP" Dendian="Little-endian" Dclock="204000000"/>
48+
<memory id="IROM1" start="0x08000000" size="0x00010000" default="1" startup="1"/>
49+
<memory id="IROM2" start="0x09000000" size="0x00010000" default="0" />
50+
<memory id="IRAM1" start="0x10000000" size="0x00010000" default="1" />
51+
<memory id="IRAM2" start="0x20000000" size="0x00010000" default="0" />
52+
</device>
53+
4554
<!-- ****************************** TestDeviceOk ***************************** -->
4655
<device Dname="TestDeviceOk">
4756
<processor Dcore="Cortex-M4" DcoreVersion="r0p1" Dfpu="SP_FPU" Dmpu="MPU" Ddsp="NO_DSP" Dendian="Little-endian" Dclock="204000000"/>

tools/projmgr/include/ProjMgrParser.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -424,15 +424,15 @@ struct CdefaultItem {
424424
* @brief debugger item containing
425425
* name of debug configuration
426426
* brief description
427-
* debug port (jtag or swd)
427+
* debug protocol (jtag or swd)
428428
* debug clock speed
429429
* debug configuration file
430430
* type filter
431431
*/
432432
struct DebuggerItem {
433433
std::string name;
434434
std::string info;
435-
std::string port;
435+
std::string protocol;
436436
std::string clock;
437437
std::string dbgconf;
438438
TypeFilter type;

tools/projmgr/include/ProjMgrRunDebug.h

Lines changed: 67 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -9,17 +9,23 @@
99

1010
#include "ProjMgrWorker.h"
1111

12+
/**
13+
* @brief ram type
14+
*/
15+
struct RamType {
16+
unsigned long long start = 0;
17+
unsigned long long size = 0;
18+
std::string pname;
19+
};
20+
1221
/**
1322
* @brief programming algorithm types
1423
*/
1524
struct AlgorithmType {
1625
std::string algorithm;
1726
unsigned long long start = 0;
1827
unsigned long long size = 0;
19-
unsigned long long ramStart = 0;
20-
unsigned long long ramSize = 0;
21-
bool bDefault = false;
22-
std::string pname;
28+
RamType ram;
2329
};
2430

2531
/**
@@ -32,9 +38,6 @@ struct MemoryType {
3238
std::string fromPack;
3339
unsigned long long start = 0;
3440
unsigned long long size = 0;
35-
bool bDefault = false;
36-
bool bStartup = false;
37-
bool bUninit = false;
3841
std::string pname;
3942
};
4043

@@ -65,7 +68,7 @@ struct DebugSequencesBlockType {
6568
std::string execute;
6669
std::string control_if;
6770
std::string control_while;
68-
std::string timeout;
71+
std::optional<unsigned int>timeout;
6972
bool bAtomic = false;
7073
std::vector<DebugSequencesBlockType> blocks;
7174
};
@@ -93,11 +96,62 @@ struct DebugVarsType {
9396
struct DebuggerType {
9497
std::string name;
9598
std::string info;
96-
std::string port;
99+
std::string protocol;
97100
unsigned long long clock = 0;
98101
std::string dbgconf;
99102
};
100103

104+
/**
105+
* @brief punit type
106+
*/
107+
struct PunitType {
108+
std::optional<unsigned int> punit;
109+
std::optional<unsigned long long> address;
110+
};
111+
112+
/**
113+
* @brief processor type
114+
*/
115+
struct ProcessorType {
116+
std::string pname;
117+
std::vector<PunitType> punits;
118+
std::optional<unsigned int> apid;
119+
std::string resetSequence;
120+
};
121+
122+
/**
123+
* @brief access port type
124+
*/
125+
struct AccessPortType {
126+
unsigned int apid;
127+
std::optional<unsigned int> index;
128+
std::optional<unsigned long long> address;
129+
std::optional<unsigned int> hprot;
130+
std::optional<unsigned int> sprot;
131+
std::vector<AccessPortType> accessPorts;
132+
};
133+
134+
/**
135+
* @brief debug port type
136+
*/
137+
struct DebugPortType {
138+
unsigned int dpid;
139+
std::optional<unsigned int> jtagTapIndex;
140+
std::optional<unsigned int> swdTargetSel;
141+
std::vector<AccessPortType> accessPorts;
142+
};
143+
144+
/**
145+
* @brief debug topology type
146+
*/
147+
struct DebugTopologyType {
148+
std::vector<DebugPortType> debugPorts;
149+
std::vector<ProcessorType> processors;
150+
std::optional<bool> swj;
151+
std::optional<bool> dormant;
152+
std::string sdf;
153+
};
154+
101155
/**
102156
* @brief debug run manager types
103157
*/
@@ -117,6 +171,7 @@ struct RunDebugType {
117171
std::vector<DebuggerType> debuggers;
118172
DebugVarsType debugVars;
119173
std::vector<DebugSequencesType> debugSequences;
174+
DebugTopologyType debugTopology;
120175
};
121176

122177
/**
@@ -154,6 +209,9 @@ class ProjMgrRunDebug {
154209
const RteItem* item, const std::string pname);
155210
FilesType SetLoadFromOutput(const ContextItem* context, OutputType output, const std::string type);
156211
std::string GetAccessAttributes(const RteItem* mem);
212+
void SetAccessPorts(std::vector<AccessPortType>& parent, const std::map<unsigned int,
213+
std::vector<AccessPortType>>& childrenMap);
214+
void SetProtNodes(const RteDeviceProperty* item, AccessPortType& ap);
157215
};
158216

159217
#endif // PROJMGRRUNDEBUG_H

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