Error M382vs64bit 1264 (#1177) (#2013)

* [svdconv] Wrong error message: *** ERROR M382:  #1264

* changed to uint

* fixed check for 64 bit wide register

* added test

Co-authored-by: Thorsten de Buhr <thorstendb-ARM@users.noreply.github.com>

Author: grasci-arm

tools/svdconv/SVDModel/include/SvdRegister.h

@@ -6,6 +6,7 @@
 #ifndef SvdRegister_H
 #define SvdRegister_H
 
+#include "SvdItem.h"
 #include "SvdTypes.h"
 
 

tools/svdconv/SVDModel/src/SvdRegister.cpp

@@ -695,7 +695,13 @@ bool SvdRegister::CheckItem()
     Invalidate();
   }
 
-  const auto maxRegValue = ((uint64_t)1 << regWidth) -1;
+  // Officially supported register size 1..32 bits. Unofficial "support" (and max value) for 64 bits.
+  uint64_t maxRegValue = 0;
+  if(regWidth < 64) {
+    maxRegValue = (uint64_t)0x1 << regWidth;
+  }
+  maxRegValue -= 1;
+
   if(resetValue > maxRegValue) {
     LogMsg("M382", LEVEL("Register"), NAME(name), NAME2("Reset Value"), HEXNUM(resetValue), NUM(regWidth), lineNo);
     SetResetValue(0);

tools/svdconv/Test/data/ResetMask/ResetMask.svd

@@ -0,0 +1,89 @@
+<?xml version="1.0" encoding="utf-8"?>
+<device xmlns:xsi="http://www.w3.org/2001/XMLSchema" schemaVersion="0">
+  <vendor>TestVendor</vendor>
+  <vendorID>Arm</vendorID>
+  <name>ResetMask</name>
+  <series>TEST</series>
+  <version>100</version>
+  <description>Default</description>
+  <licenseText>Test case</licenseText>
+  <cpu>
+    <name>other</name>
+    <revision>r0p0</revision>
+    <endian>little</endian>
+    <mpuPresent>true</mpuPresent>
+    <fpuPresent>true</fpuPresent>
+    <nvicPrioBits>4</nvicPrioBits>
+    <vendorSystickConfig>true</vendorSystickConfig>
+  </cpu>
+  <addressUnitBits>8</addressUnitBits>
+  <width>8</width>
+  <peripherals>
+    <peripheral>
+      <name>RESET_MASK</name>
+      <version>100</version>
+      <description>RESET MASK</description>
+      <groupName>RESET_MASK</groupName>
+      <baseAddress>0</baseAddress>
+      <addressBlock>
+        <offset>0</offset>
+        <size>12</size>
+        <usage>registers</usage>
+      </addressBlock>
+      <registers>
+        <register>
+          <name>TIMER</name>
+          <description>Timer TestReg</description>
+          <addressOffset>0</addressOffset>
+          <size>64</size>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFFFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>TIMER</name>
+              <description>System timer bits.</description>
+              <lsb>0</lsb>
+              <msb>63</msb>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TIMER2</name>
+          <description>Timer TestReg</description>
+          <addressOffset>0</addressOffset>
+          <size>65</size>
+          <resetValue>0</resetValue>
+          <resetMask>0xFFFFFFFFFFFFFFFF</resetMask>
+          <fields>
+            <field>
+              <name>TIMER</name>
+              <description>System timer bits.</description>
+              <lsb>0</lsb>
+              <msb>63</msb>
+              <access>read-write</access>
+            </field>
+          </fields>
+        </register>
+        <register>
+          <name>TestRegister</name>
+          <description>TestRegister</description>
+          <addressOffset>8</addressOffset>
+          <size>32</size>
+          <resetValue>0</resetValue>
+          <resetMask>4294967295</resetMask>
+          <fields>
+            <field>
+              <name>TestBitfield</name>
+              <description>TestBitfield</description>
+              <lsb>0</lsb>
+              <msb>31</msb>
+              <access>read-write</access>
+              <modifiedWriteValues>oneToClear</modifiedWriteValues>
+            </field>
+          </fields>
+        </register>
+      </registers>
+    </peripheral>
+  </peripherals>
+</device>

tools/svdconv/Test/integtests/src/SvdConvIntegTests.cpp

@@ -158,7 +158,6 @@ TEST_F(SvdConvIntegTests, CheckSauNumRegions_Errors) {
   }
 }
 
-// Validate NameHasBrackets
 TEST_F(SvdConvIntegTests, CheckAccViolationDisableCond) {
   const string& inFile = SvdConvIntegTestEnv::localtestdata_dir + "/accViolationDisableCond/accViolationDisableCond.xml";
   ASSERT_TRUE(RteFsUtils::Exists(inFile));
@@ -168,3 +167,39 @@ TEST_F(SvdConvIntegTests, CheckAccViolationDisableCond) {
   SvdConv svdConv;
   EXPECT_EQ(1, svdConv.Check(args, args, nullptr));
 }
+
+TEST_F(SvdConvIntegTests, CheckResetMask) {
+  const string& inFile = SvdConvIntegTestEnv::localtestdata_dir + "/ResetMask/ResetMask.svd";
+  ASSERT_TRUE(RteFsUtils::Exists(inFile));
+
+  Arguments args("SVDConv.exe", inFile);
+
+  SvdConv svdConv;
+  EXPECT_EQ(1, svdConv.Check(args, args, nullptr));
+
+  struct {
+    int M318 = 0;
+    int M351 = 0;
+    int M356 = 0;
+  } cnt;
+
+  auto errMsgs = ErrLog::Get()->GetLogMessages();
+  for (const string& msg : errMsgs) {
+    size_t s;
+
+    if ((s = msg.find("M318", 0)) != string::npos) {
+      cnt.M318++;
+    }
+    if ((s = msg.find("M351", 0)) != string::npos) {
+      cnt.M351++;
+    }
+    if ((s = msg.find("M356", 0)) != string::npos) {
+      cnt.M356++;
+    }
+  }
+
+  if(cnt.M318 != 2 || cnt.M351 != 1 || cnt.M356 != 1) {
+    FAIL() << "Occurrences of M318, M351, M356 are wrong.";
+  }
+}
+